Zhixiong Di

39 papers A* 1Journal 31Unranked 7
YearRankTypeTitle / Venue / Authors
2026 J jnl
LEGALM 2.0: A Versatile Augmented Lagrangian Method-Based Methodology for Mixed-Cell-Height Legalization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jing Mai, Chunyuan Zhao, Zuodong Zhang, Zhixiong Di, Runsheng Wang, Yibo Lin
2025 J jnl
A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xun Jiang, Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin
2025 J jnl
An r-DFA-Based Layout Pattern Match Method Supporting Fuzzy Matching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qianxi Chen, Yujiao Deng, Qiang Wu, Zhixiong Di
2025 J jnl
Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs.
CoRR
He Jiang, Yi Guo, Shikai Guo, Huijiang Liu, Xiaochen Li, Ning Wang, Zhixiong Di
2025 J jnl
Efficient Schemes and Architectures for Check Node Update in Shuffled Min-Sum Decoding of LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Lisha Luo, Xuan He, Qin Du, Kaining Han, Zhixiong Di, Xiaohu Tang
2025 — conf
LEGALM: Efficient Legalization for Mixed-Cell-Height Circuits with Linearized Augmented Lagrangian Method.
ISPD
Jing Mai, Chunyuan Zhao, Zuodong Zhang, Zhixiong Di, Yibo Lin, Runsheng Wang, Ru Huang
2025 J jnl
RELIC-GNN: Efficient State Registers Identification with Graph Neural Network for Reverse Engineering.
CoRR
Weitao Pan, Meng Dong, Zhiliang Qiu, Jianlei Yang, Zhixiong Di, Yiming Gao
2024 — conf
A Remote FPGA-based Experimental Teaching System Design Supporting Single-board Multi-user and Multi-board Single-user Operations in MOOCs.
ACM Great Lakes Symposium on VLSI
Zhixiong Di, Xufeng Wei, Yiduo Chen, Shuanglong Wu, Peihao Sun, Qiang Wu
2024 J jnl
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction.
IEEE Trans. Circuits Syst. II Express Briefs
Zhixiong Di, Runzhe Tao, Lin Chen, Qiang Wu, Yibo Lin
2024 J jnl
LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhixiong Di, Runzhe Tao, Jing Mai, Lin Chen, Yibo Lin
2024 J jnl
Multielectrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jing Mai, Jiarui Wang, Zhixiong Di, Yibo Lin
2024 J jnl
Semi-Supervised Transfer Learning Framework for Aging-Aware Library Characterization.
IEEE Trans. Circuits Syst. II Express Briefs
Zhengguang Tang, Cong Li, Hailong You, Zhixiong Di, Linying Zhang, Xingming Liu, Yu Wang, Yong Dai, Geng Bai
2023 J jnl
A High Precision CV Control Scheme for Low Power AC-DC BUCK Converter Controller.
IEEE Trans. Circuits Syst. I Regul. Pap.
Qiang Wu, Linjun Wu, Yongyuan Li, Xun Li, Zhixiong Di, Shubin Liu, Zhangming Zhu
2023 — conf
A Robust FPGA Router with Concurrent Intra-CLB Rerouting.
ASP-DAC
Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin
2023 J jnl
A unioned graph neural network based hardware Trojan node detection.
IEICE Electron. Express
Weitao Pan, Meng Dong, Cong Wen, Hongjin Liu, Shaolin Zhang, Bo Shi, Zhixiong Di, Zhiliang Qiu, Yiming Gao, Ling Zheng
2023 J jnl
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction.
CoRR
Zhixiong Di, Runzhe Tao, Lin Chen, Qiang Wu, Yibo Lin
2023 J jnl
LEAPS: Topological-Layout-Adaptable Multi-die FPGA Placement for Super Long Line Minimization.
CoRR
Zhixiong Di, Runzhe Tao, Jing Mai, Lin Chen, Yibo Lin
2023 J jnl
Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization.
CoRR
Jing Mai, Jiarui Wang, Zhixiong Di, Yibo Lin
2023 — conf
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit.
ASICON
Jing Mai, Jiarui Wang, Zhixiong Di, Guojie Luo, Yun Liang, Yibo Lin
2023 J jnl
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit.
CoRR
Jing Mai, Jiarui Wang, Zhixiong Di, Guojie Luo, Yun Liang, Yibo Lin
2022 J jnl
A High Throughput and Energy Efficient Lepton Hardware Encoder With Hash-Based Memory Optimization.
IEEE Trans. Circuits Syst. Video Technol.
Xiao Yan, Zhixiong Di, Bowen Huang, Minjiang Li, Wenqiang Wang, Xiaoyang Zeng, Yibo Fan
2022 J jnl
A High-Throughput VLSI Architecture Design of Canonical Huffman Encoder.
IEEE Trans. Circuits Syst. II Express Briefs
Zhenyu Shao, Zhixiong Di, Quanyuan Feng, Qiang Wu, Yibo Fan, Xulin Yu, Wenqiang Wang
2022 J jnl
A Valley-Locking Control Scheme for an Audible Noise-Free Valley-Skip-Mode Flyback Converter.
IEEE Trans. Ind. Electron.
Qiang Wu, Xun Li, Yueyun Han, Zhixiong Di, Quanyuan Feng
2022 J jnl
Detailed Routing Short Violation Prediction Using Graph-Based Deep Learning Model.
IEEE Trans. Circuits Syst. II Express Briefs
Xuan Chen, Zhixiong Di, Wei Wu, Qiang Wu, Jiangyi Shi, Quanyuan Feng
2022 J jnl
Implementation of High Precision Error Amplification Scheme for AC-DC Converter.
IEEE Trans. Circuits Syst. II Express Briefs
Qiang Wu, Xun Li, Yongyuan Li, Zhixiong Di, Quanyuan Feng
2022 J jnl
Learned Compression Framework With Pyramidal Features and Quality Enhancement for SAR Images.
IEEE Geosci. Remote. Sens. Lett.
Zhixiong Di, Xuan Chen, Qiang Wu, Jiangyi Shi, Quanyuan Feng, Yibo Fan
2022 A* conf
Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility.
DAC
Jing Mai, Yibai Meng, Zhixiong Di, Yibo Lin
2022 J jnl
NBLG: A Robust Legalizer for Mixed-Cell-Height Modern Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jinwei Chen, Zhixiong Di, Jiangyi Shi, Quanyuan Feng, Qiang Wu
2022 J jnl
Synthetic Aperture Radar Image Compression Based on a Variational Autoencoder.
IEEE Geosci. Remote. Sens. Lett.
Qihan Xu, Yunfan Xiang, Zhixiong Di, Yibo Fan, Quanyuan Feng, Qiang Wu, Jiangyi Shi
2021 J jnl
A Power and Area Efficient Lepton Hardware Encoder with Hash-based Memory Optimization.
CoRR
Xiao Yan, Zhixiong Di, Bowen Huang, Minjiang Li, Wenqiang Wang, Xiaoyang Zeng, Yibo Fan
2021 — conf
ASIC Design Principle Course with Combination of Online-MOOC and Offline-Inexpensive FPGA Board.
ACM Great Lakes Symposium on VLSI
Zhixiong Di, Yongming Tang, Jiahua Lu, Zhaoyang Lv
2020 J jnl
A local congestion elimination technique driven by overflow.
IEICE Electron. Express
Wei Wu, Zhixiong Di, Jiangyi Shi, Quanyuan Feng, Zhengguang Tang
2020 J jnl
A self-clocked binary-seaching digital low-dropout regulator with fast transient response.
IEICE Electron. Express
Jiangyi Shi, Bo Zhao, Zhengguang Tang, Peijun Ma, Zhixiong Di
2019 J jnl
A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design.
IEEE Trans. Circuits Syst. II Express Briefs
Yinghui Tian, Yong Hei, Zhizhe Liu, Qi Shen, Zhixiong Di, Tao Chen
2019 — conf
High Parallel VLSI Architecture Design of BPC in JPEG2000.
ASICON
Lintao Li, Jiangyi Shi, Zhixiong Di
2017 J jnl
A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes.
IEICE Electron. Express
Yinghui Tian, Yong Hei, Zhizhe Liu, Zhixiong Di, Qi Shen, Zenghui Yu
2017 J jnl
Erratum: A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes [IEICE Electronics Express Vol. 14 (2017) No. 15 pp. 20170660].
IEICE Electron. Express
Yinghui Tian, Yong Hei, Zhizhe Liu, Zhixiong Di, Qi Shen, Zenghui Yu
2015 J jnl
A High-Throughput VLSI Architecture Design of Arithmetic Encoder in JPEG2000.
J. Signal Process. Syst.
Zhixiong Di, Yue Hao, Jiangyi Shi, Peijun Ma
2015 — conf
LC-KO: A congestion-aware and area&timing-oriented placement method.
ASICON
Zhixiong Di, Yanlong Wang, Shuang Qiao, Qianyin Xiang, Quanyuan Feng