Zhixian Deng

14 papers Journal 8Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
Dense object detection via contrastive learning representations and reinforcement learning decisions.
Inf. Sci.
Huanrong Tang, Zhixian Deng, Jianquan Ouyang
2024 J jnl
A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Changxuan Han, Zhixian Deng, Yiyang Shu, Jun Yin, Pui-In Mak, Xun Luo
2024 J jnl
A Phased-Array Transceiver With 2-Dimension Continuously Auto Link-Tracking Operation and Time Division Modulator.
IEEE J. Solid State Circuits
Xun Luo, Bingzheng Yang, Zhixian Deng, Wen Chen, Yiyang Shu, Jie Zhou
2023 — conf
71-to-89GHz 12Gb/s Double-Edge-Triggered Quadrature RFDAC with LO Leakage Suppression Achieving 20.5dBm Peak Output Power and 20.4% System Efficiency.
ISSCC
Bingzheng Yang, Zhixian Deng, Huizhen Jenny Qian, Xun Luo
2023 J jnl
A 23-40-GHz Phased-Array Receiver Using 14-Bit Phase-Gain Manager and Wideband Noise-Canceling LNA.
IEEE J. Solid State Circuits
Zhixian Deng, Changxuan Han, Yifan Li, Huizhen Jenny Qian, Xun Luo
2023 — conf
A 28GHz Scalable Inter-Core-Shaping Multi-Core Oscillator with DM/CM-Configured Coupling Achieving 193.3dBc/Hz FoM and 205.5dBc/Hz FoMA at 1MHz Offset.
ISSCC
Yiyang Shu, Zhixian Deng, Xun Luo
2023 — conf
A 4.8dB NF, 70-to-86GHz Deep-Noise-Canceling LNA Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner in 40nm CMOS.
ISSCC
Changxuan Han, Jie Zhou, Zhixian Deng, Yiyang Shu, Xun Luo
2023 — conf
An 8-Element 23-40 GHz Continuously Auto Link-Tracking Phased-Array Transceiver with Time Division Modulator Achieving 7μs Tracking Time, 25.3% TX System Efficiency, 800MHz-64QAM Modulation for 5G NR.
CICC
Zhixian Deng, Bingzheng Yang, Wen Chen, Jie Zhou, Changxuan Han, Yifan Li, Yiyang Shu, Xun Luo
2022 — conf
A 3.8-dB NF, 23-40GHz Phased-Array Receiver with 14-Bit Phase & Gain Manager and Calibration-Free Dual-Mode 28-52dB Image Rejection Ratio for 5G NR.
CICC
Zhixian Deng, Huizhen Jenny Qian, Changxuan Han, Yifan Li, Xun Luo
2022 J jnl
A Reflectionless Receiver With Absorptive IF Amplifier and Dual-Path Noise-Canceling LNA.
IEEE J. Solid State Circuits
Zhixian Deng, Huizhen Jenny Qian, Xun Luo
2022 J jnl
Compact SIDGS Filtering Power Divider With Three-Port 10-GHz Reflectionless Range.
IEEE Trans. Circuits Syst. II Express Briefs
Qingxian Li, Hongxin Tang, Deshan Tang, Zhixian Deng, Xun Luo
2021 J jnl
A 22.9-38.2-GHz Dual-Path Noise-Canceling LNA With 2.65-4.62-dB NF in 28-nm CMOS.
IEEE J. Solid State Circuits
Zhixian Deng, Jie Zhou, Huizhen Jenny Qian, Xun Luo
2021 — conf
A 3.6dB NF, 23-39GHz Reflectionless RX with Absorptive Amplifier and Dual-Path Noise Cancelling LNA Supporting 64-QAM/256-QAM/1024-QAM for 5G NR.
CICC
Zhixian Deng, Huizhen Jenny Qian, Xun Luo
2019 J jnl
Tunable Quasi-Circulator Based on a Compact Fully-Reconfigurable 180° Hybrid for Full-Duplex Transceivers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhixian Deng, Huizhen Jenny Qian, Xun Luo