Zhiru Zhang - RankMe

215 papers A* 48A 49B 1Misc 10Journal 86Unranked 21

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	From Pragmas to Partners: A Symbiotic Evolution of Agentic High-Level Synthesis. CoRR Niansong Zhang, Sunwoo Kim, Shreesha Srinath, Zhiru Zhang
2026	J	`jnl`	GauS: Differentiable Scheduling Optimization via Gaussian Reparameterization. CoRR Yaohui Cai, Vesal Bakhtazad, Cunxi Yu, Zhiru Zhang
2026	J	`jnl`	Magellan: Autonomous Discovery of Novel Compiler Optimization Heuristics with AlphaEvolve. CoRR Hongzheng Chen, Alexander Novikov, Ngân Vu, Hanna Alam, Zhiru Zhang, Aiden Grossman, Mircea Trofin, Amir Yazdanbakhsh
2026	A	`conf`	Tawa: Automatic Warp Specialization for Modern GPUs with Asynchronous References. CGO Hongzheng Chen, Bin Fan, Alexander Collins, Bastian Hagedorn, Evghenii Gaburov, Masahiro Masuda, Matthew Brookhart, Chris Sullivan, Jason Knight, Zhiru Zhang, Vinod Grover
2025	A	`conf`	ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines. FPGA Jinming Zhuang, Shaojie Xiang, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou
2025	—	`conf`	ASPEN: LLM-Guided E-Graph Rewriting for RTL Datapath Optimization. MLCAD Niansong Zhang, Chenhui Deng, Johannes Maximilian Kühn, Chia-Tung Ho, Cunxi Yu, Zhiru Zhang, Haoxing Ren
2025	J	`jnl`	Accelerating Diffusion Language Model Inference via Efficient KV Caching and Guided Diffusion. CoRR Zhanqiu Hu, Jian Meng, Yash Akhauri, Mohamed S. Abdelfattah, Jae-sun Seo, Zhiru Zhang, Udit Gupta
2025	A*	`conf`	Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device. MICRO Niansong Zhang, Wenbo Zhu, Courtney Golden, Dan Ilan, Hongzheng Chen, Christopher Batten, Zhiru Zhang
2025	J	`jnl`	Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device. CoRR Niansong Zhang, Wenbo Zhu, Courtney Golden, Dan Ilan, Hongzheng Chen, Christopher Batten, Zhiru Zhang
2025	A*	`conf`	CirSTAG: Circuit Stability Analysis on Graph-based Manifolds. DAC Wuxinlin Cheng, Yihang Yuan, Chenhui Deng, Ali Aghdaei, Zhiru Zhang, Zhuo Feng
2025	—	`conf`	Cypress: VLSI-Inspired PCB Placement with GPU Acceleration. ISPD Niansong Zhang, Anthony Agnesina, Noor Shbat, Yuval Leader, Zhiru Zhang, Haoxing Ren
2025	J	`jnl`	Dato: A Task-Based Programming Model for Dataflow Accelerators. CoRR Shihan Fang, Hongzheng Chen, Niansong Zhang, Jiajie Li, Han Meng, Adrian Liu, Zhiru Zhang
2025	A	`conf`	EqMap: FPGA LUT Remapping using E-Graphs. ICCAD Matthew Hofmann, Berk Gokmen, Zhiru Zhang
2025	—	`conf`	Graph Learning at Scale: Characterizing and Optimizing Pre-Propagation GNNs. MLSys Zichao Yue, Chenhui Deng, Zhiru Zhang
2025	J	`jnl`	Graph Learning at Scale: Characterizing and Optimizing Pre-Propagation GNNs. CoRR Zichao Yue, Chenhui Deng, Zhiru Zhang
2025	J	`jnl`	HeuriGym: An Agentic Benchmark for LLM-Crafted Heuristics in Combinatorial Optimization. CoRR Hongzheng Chen, Yingheng Wang, Yaohui Cai, Hins Hu, Jiajie Li, Shirley Huang, Chenhui Deng, Rongjian Liang, Shufeng Kong, Haoxing Ren, Samitha Samaranayake, Carla P. Gomes, Zhiru Zhang
2025	J	`jnl`	PIMsynth: A Unified Compiler Framework for Bit-Serial Processing-in-Memory Architectures. IEEE Comput. Archit. Lett. Deyuan Guo, MohammadHosein Gholamrezaei, Matthew Hofmann, Ashish Venkat, Zhiru Zhang, Kevin Skadron
2025	J	`jnl`	Semantic Compression of 3D Objects for Open and Collaborative Virtual Worlds. CoRR Jordan Dotzel, Tony Montes, Mohamed S. Abdelfattah, Zhiru Zhang
2025	—	`conf`	SmoothE: Differentiable E-Graph Extraction. ASPLOS (1) Yaohui Cai, Kaixin Yang, Chenhui Deng, Cunxi Yu, Zhiru Zhang
2025	J	`jnl`	Tawa: Automatic Warp Specialization for Modern GPUs with Asynchronous References. CoRR Hongzheng Chen, Bin Fan, Alexander Collins, Bastian Hagedorn, Evghenii Gaburov, Masahiro Masuda, Matthew Brookhart, Chris Sullivan, Jason Knight, Zhiru Zhang, Vinod Grover
2025	J	`jnl`	Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference. ACM Trans. Reconfigurable Technol. Syst. Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang
2025	J	`jnl`	Vesper: A Versatile Sparse Linear Algebra Accelerator With Configurable Compute Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hanchen Jin, Zichao Yue, Zhongyuan Zhao, Yixiao Du, Chenhui Deng, Nitish Srivastava, Zhiru Zhang
2025	A	`conf`	e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving. ICCAD Jiaqi Yin, Zhan Song, Chen Chen, Yaohui Cai, Zhiru Zhang, Cunxi Yu
2025	J	`jnl`	e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving. CoRR Jiaqi Yin, Zhan Song, Chen Chen, Yaohui Cai, Zhiru Zhang, Cunxi Yu
2024	A	`conf`	A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs. FPGA Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang
2024	J	`jnl`	Allo: A Programming Model for Composable Accelerator Design. CoRR Hongzheng Chen, Niansong Zhang, Shaojie Xiang, Zhichen Zeng, Mengjia Dai, Zhiru Zhang
2024	J	`jnl`	Allo: A Programming Model for Composable Accelerator Design. Proc. ACM Program. Lang. Hongzheng Chen, Niansong Zhang, Shaojie Xiang, Zhichen Zeng, Mengjia Dai, Zhiru Zhang
2024	A*	`conf`	Differentiable Combinatorial Scheduling at Scale. ICML Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu
2024	J	`jnl`	Differentiable Combinatorial Scheduling at Scale. CoRR Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu
2024	—	`conf`	Exploring the Limits of Semantic Image Compression at Micro-bits per Pixel. Tiny Papers @ ICLR Jordan Dotzel, Bahaa Kotb, James Dotzel, Mohamed S. Abdelfattah, Zhiru Zhang
2024	J	`jnl`	Exploring the Limits of Semantic Image Compression at Micro-bits per Pixel. CoRR Jordan Dotzel, Bahaa Kotb, James Dotzel, Mohamed S. Abdelfattah, Zhiru Zhang
2024	—	`conf`	FLIQS: One-Shot Mixed-Precision Floating-Point and Integer Quantization Search. AutoML Jordan Dotzel, Gang Wu, Andrew Li, Muhammad Umar, Yun Ni, Mohamed S. Abdelfattah, Zhiru Zhang, Liqun Cheng, Martin G. Dixon, Norman P. Jouppi, Quoc V. Le, Sheng Li
2024	A	`conf`	Formal Verification of Source-to-Source Transformations for HLS. FPGA Louis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodríguez, Zhiru Zhang
2024	A*	`conf`	Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs. ICML Jordan Dotzel, Yuzong Chen, Bahaa Kotb, Sushma Prasad, Gang Wu, Sheng Li, Mohamed S. Abdelfattah, Zhiru Zhang
2024	J	`jnl`	Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs. CoRR Jordan Dotzel, Yuzong Chen, Bahaa Kotb, Sushma Prasad, Gang Wu, Sheng Li, Mohamed S. Abdelfattah, Zhiru Zhang
2024	A*	`conf`	Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits. DAC Chenhui Deng, Zichao Yue, Cunxi Yu, Gokce Sarar, Ryan Carey, Rajeev Jain, Zhiru Zhang
2024	J	`jnl`	Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits. CoRR Chenhui Deng, Zichao Yue, Cunxi Yu, Gokce Sarar, Ryan Carey, Rajeev Jain, Zhiru Zhang
2024	A*	`conf`	LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space Scheduling. HPCA Yueying Li, Nikita Lazarev, David Koufaty, Tenny Yin, Andy Anderson, Zhiru Zhang, G. Edward Suh, Kostis Kaffes, Christina Delimitrou
2024	J	`jnl`	Pangenome graph layout by Path-Guided Stochastic Gradient Descent. Bioinform. Simon Heumos, Andrea Guarracino, Jan-Niklas Schmelzle, Jiajie Li, Zhiru Zhang, Jörg Hagmann, Sven Nahnsen, Pjotr Prins, Erik Garrison
2024	A*	`conf`	Polynormer: Polynomial-Expressive Graph Transformer in Linear Time. ICLR Chenhui Deng, Zichao Yue, Zhiru Zhang
2024	J	`jnl`	Polynormer: Polynomial-Expressive Graph Transformer in Linear Time. CoRR Chenhui Deng, Zichao Yue, Zhiru Zhang
2024	A	`ed.`	Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024 FPGA Zhiru Zhang, Andrew Putnam
2024	J	`jnl`	Radial Networks: Dynamic Layer Routing for High-Performance Large Language Models. CoRR Jordan Dotzel, Yash Akhauri, Ahmed S. AbouElhamayed, Carly Jiang, Mohamed S. Abdelfattah, Zhiru Zhang
2024	A	`conf`	Rapid GPU-Based Pangenome Graph Layout. SC Jiajie Li, Jan-Niklas Schmelzle, Yixiao Du, Simon Heumos, Andrea Guarracino, Giulia Guidi, Pjotr Prins, Erik Garrison, Zhiru Zhang
2024	J	`jnl`	Rapid GPU-Based Pangenome Graph Layout. CoRR Jiajie Li, Jan-Niklas Schmelzle, Yixiao Du, Simon Heumos, Andrea Guarracino, Giulia Guidi, Pjotr Prins, Erik Garrison, Zhiru Zhang
2024	A	`conf`	RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. ICCAD Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo
2024	J	`jnl`	RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. CoRR Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo
2024	J	`jnl`	SAGMAN: Stability Analysis of Graph Neural Networks on the Manifolds. CoRR Wuxinlin Cheng, Chenhui Deng, Ali Aghdaei, Zhiru Zhang, Zhuo Feng
2024	A*	`conf`	Sabre: Hardware-Accelerated Snapshot Compression for Serverless MicroVMs. OSDI Nikita Lazarev, Varun Gohil, James Tsai, Andy Anderson, Bhushan Chitlur, Zhiru Zhang, Christina Delimitrou
2024	A*	`conf`	Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. ISCA Dai Cheol Jung, Max Ruttenberg, Paul Gao, Scott Davidson, Daniel Petrisko, Kangli Li, Aditya K. Kamath, Lin Cheng, Shaolin Xie, Peitian Pan, Zhongyuan Zhao, Zichao Yue, Bandhav Veluri, Sripathi Muralitharan, Adrian Sampson, Andrew Lumsdaine, Zhiru Zhang, Christopher Batten, Mark Oskin, Dustin Richmond, Michael Bedford Taylor
2024	A*	`conf`	ShadowLLM: Predictor-based Contextual Sparsity for Large Language Models. EMNLP Yash Akhauri, Ahmed F. AbouElhamayed, Jordan Dotzel, Zhiru Zhang, Alexander M. Rush, Safeen Huda, Mohamed S. Abdelfattah
2024	J	`jnl`	ShadowLLM: Predictor-based Contextual Sparsity for Large Language Models. CoRR Yash Akhauri, Ahmed F. AbouElhamayed, Jordan Dotzel, Zhiru Zhang, Alexander M. Rush, Safeen Huda, Mohamed S. Abdelfattah
2024	—	`conf`	Slapo: A Schedule Language for Progressive Optimization of Large Deep Learning Model Training. ASPLOS (2) Hongzheng Chen, Cody Hao Yu, Shuai Zheng, Zhen Zhang, Zhiru Zhang, Yida Wang
2024	J	`jnl`	Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator. IEEE Comput. Archit. Lett. Courtney Golden, Dan Ilan, Caroline Huang, Niansong Zhang, Zhiru Zhang, Christopher Batten
2024	J	`jnl`	Trainable Fixed-Point Quantization for Deep Learning Acceleration on FPGAs. CoRR Dingyi Dai, Yichi Zhang, Jiahao Zhang, Zhanqiu Hu, Yaohui Cai, Qi Sun, Zhiru Zhang
2024	J	`jnl`	UniSparse: An Intermediate Language for General Sparse Format Customization. CoRR Jie Liu, Zhongyuan Zhao, Zijian Ding, Benjamin Brock, Hongbo Rong, Zhiru Zhang
2024	J	`jnl`	UniSparse: An Intermediate Language for General Sparse Format Customization. Proc. ACM Program. Lang. Jie Liu, Zhongyuan Zhao, Zijian Ding, Benjamin Brock, Hongbo Rong, Zhiru Zhang
2023	J	`jnl`	A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. IEEE J. Solid State Circuits Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo
2023	—	`conf`	A Case for Open EDA Verticals. ISPD Zhiru Zhang, Matthew Hofmann, Andrew Butt
2023	J	`jnl`	An Intermediate Language for General Sparse Format Customization. IEEE Comput. Archit. Lett. Jie Liu, Zhongyuan Zhao, Zijian Ding, Benjamin Brock, Hongbo Rong, Zhiru Zhang
2023	A*	`conf`	Binarized Neural Machine Translation. NeurIPS Yichi Zhang, Ankush Garg, Yuan Cao, Lukasz Lew, Behrooz Ghorbani, Zhiru Zhang, Orhan Firat
2023	J	`jnl`	Binarized Neural Machine Translation. CoRR Yichi Zhang, Ankush Garg, Yuan Cao, Lukasz Lew, Behrooz Ghorbani, Zhiru Zhang, Orhan Firat
2023	J	`jnl`	Comprehensive Benchmarking of Binary Neural Networks on NVM Crossbar Architectures. CoRR Ruirong Huang, Zichao Yue, Caroline Huang, Janarbek Matai, Zhiru Zhang
2023	J	`jnl`	Decoupled Model Schedule for Deep Learning Training. CoRR Hongzheng Chen, Cody Hao Yu, Shuai Zheng, Zhen Zhang, Zhiru Zhang, Yida Wang
2023	A*	`conf`	Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality. DAC Ecenur Ustun, Cunxi Yu, Zhiru Zhang
2023	J	`jnl`	FLIQS: One-Shot Mixed-Precision Floating-Point and Integer Quantization Search. CoRR Jordan Dotzel, Gang Wu, Andrew Li, Muhammad Umar, Yun Ni, Mohamed S. Abdelfattah, Zhiru Zhang, Liqun Cheng, Martin G. Dixon, Norman P. Jouppi, Quoc V. Le, Sheng Li
2023	A	`ed.`	Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023 FPGA Paolo Ienne, Zhiru Zhang
2023	J	`jnl`	RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
2023	A*	`conf`	Resilient Baseband Processing in Virtualized RANs with Slingshot. SIGCOMM Nikita Lazarev, Tao Ji, Anuj Kalia, Daehyeok Kim, Ilias Marinos, Francis Y. Yan, Christina Delimitrou, Zhiru Zhang, Aditya Akella
2023	Misc	`conf`	Special Session: Machine Learning for Embedded System Design. CODES+ISSS Erika S. Alcorta, Andreas Gerstlauer, Chenhui Deng, Qi Sun, Zhiru Zhang, Ceyu Xu, Lisa Wu Wills, Daniela Sanchez Lopera, Wolfgang Ecker, Siddharth Garg, Jiang Hu
2023	J	`jnl`	TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. ACM Trans. Reconfigurable Technol. Syst. Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong
2023	J	`jnl`	Towards Fast, Adaptive, and Hardware-Assisted User-Space Scheduling. CoRR Yueying Li, Nikita Lazarev, David Koufaty, Yijun Yin, Andy Anderson, Zhiru Zhang, G. Edward Suh, Kostis Kaffes, Christina Delimitrou
2023	J	`jnl`	Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference. CoRR Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang
2022	—	`conf`	A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. ESSCIRC Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo
2022	J	`jnl`	A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lin Cheng, Peitian Pan, Zhongyuan Zhao, Krithik Ranjan, Jack Weber, Bandhav Veluri, Seyed Borna Ehsani, Max Ruttenberg, Dai Cheol Jung, Preslav Ivanov, Dustin Richmond, Michael B. Taylor, Zhiru Zhang, Christopher Batten
2022	A*	`conf`	Accelerator design with decoupled hardware customizations: benefits and challenges: invited. DAC Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang
2022	J	`jnl`	Benchmarking GNN-Based Recommender Systems on Intel Optane Persistent Memory. CoRR Yuwei Hu, Jiajie Li, Zhongming Yu, Zhiru Zhang
2022	Misc	`conf`	Exact Memory- and Communication-aware Scheduling of DNNs on Pipelined Edge TPUs. SEC Jiaqi Yin, Zhiru Zhang, Cunxi Yu
2022	J	`jnl`	FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Trans. Reconfigurable Technol. Syst. Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees A. Vissers, Zhiru Zhang
2022	—	`conf`	GARNET: Reduced-Rank Topology Learning for Robust and Scalable Graph Neural Networks. LoG Chenhui Deng, Xiuyu Li, Zhuo Feng, Zhiru Zhang
2022	J	`jnl`	GARNET: Reduced-Rank Topology Learning for Robust and Scalable Graph Neural Networks. CoRR Chenhui Deng, Xiuyu Li, Zhuo Feng, Zhiru Zhang
2022	A*	`conf`	GuardNN: secure accelerator architecture for privacy-preserving deep learning. DAC Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
2022	A	`conf`	HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. FPGA Shaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen, Niansong Zhang, Debjit Pal, Zhiru Zhang
2022	A	`conf`	High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV. FPGA Yixiao Du, Yuwei Hu, Zhongchun Zhou, Zhiru Zhang
2022	Misc	`conf`	IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLS. FCCM Ecenur Ustun, Ismail San, Jiaqi Yin, Cunxi Yu, Zhiru Zhang
2022	A*	`conf`	MGX: near-zero overhead memory protection for data-intensive accelerators. ISCA Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
2022	A*	`conf`	PokeBNN: A Binary Pursuit of Lightweight Accuracy. CVPR Yichi Zhang, Zhiru Zhang, Lukasz Lew
2022	A	`conf`	RapidStream: Parallel Physical Implementation of FPGA HLS Designs. FPGA Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
2022	J	`jnl`	Reverse-Engineering CNN Models Using Side-Channel Attacks. IEEE Des. Test Weizhe Hua, Zhiru Zhang, G. Edward Suh
2022	A*	`conf`	SoftVN: efficient memory protection via software-provided version numbers. ISCA Muhammad Umar, Weizhe Hua, Zhiru Zhang, G. Edward Suh
2022	J	`jnl`	Structured Pruning is All You Need for Pruning CNNs at Initialization. CoRR Yaohui Cai, Weizhe Hua, Hongzheng Chen, G. Edward Suh, Christopher De Sa, Zhiru Zhang
2022	J	`jnl`	TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design. CoRR Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong
2022	A*	`conf`	Understanding Hyperdimensional Computing for Parallel Single-Pass Learning. NeurIPS Tao Yu, Yichi Zhang, Zhiru Zhang, Christopher De Sa
2022	J	`jnl`	Understanding Hyperdimensional Computing for Parallel Single-Pass Learning. CoRR Tao Yu, Yichi Zhang, Zhiru Zhang, Christopher De Sa
2021	J	`jnl`	A Roadmap for Enabling a Future-Proof In-Network Computing Data Plane Ecosystem. CoRR Daehyeok Kim, Nikita Lazarev, Tommy Tracy II, Farzana Siddique, Hun Namkung, James C. Hoe, Vyas Sekar, Kevin Skadron, Zhiru Zhang, Srinivasan Seshan
2021	A	`conf`	AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. FPGA Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong
2021	A*	`conf`	BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. NeurIPS Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh
2021	J	`jnl`	BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. CoRR Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh
2021	J	`jnl`	Dagger: Accelerating RPCs in Cloud Microservices Through Tightly-Coupled Reconfigurable NICs. CoRR Nikita Lazarev, Shaojie Xiang, Neil Adit, Zhiru Zhang, Christina Delimitrou
2021	A*	`conf`	Dagger: efficient and fast RPCs in cloud microservices with near-memory reconfigurable NICs. ASPLOS Nikita Lazarev, Shaojie Xiang, Neil Adit, Zhiru Zhang, Christina Delimitrou
2021	J	`jnl`	Dense Pruning of Pointwise Convolutions in the Frequency Domain. CoRR Mark Buckler, Neil Adit, Yuwei Hu, Zhiru Zhang, Adrian Sampson
2021	A*	`conf`	Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC. DAC Yuan Zhou, Hanyu Wang, Jieming Yin, Zhiru Zhang
2021	J	`jnl`	Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design. CoRR Cong Hao, Jordan Dotzel, Jinjun Xiong, Luca Benini, Zhiru Zhang, Deming Chen
2021	J	`jnl`	Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign. IEEE Des. Test Cong Hao, Jordan Dotzel, Jinjun Xiong, Luca Benini, Zhiru Zhang, Deming Chen
2021	A	`conf`	FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations. FPGA Yichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen, Zhiru Zhang
2021	A	`conf`	GLAIVE: Graph Learning Assisted Instruction Vulnerability Estimation. DATE Jiajia Jiao, Debjit Pal, Chenhui Deng, Zhiru Zhang
2021	A	`conf`	GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs. ICCAD Yuwei Hu, Yixiao Du, Ecenur Ustun, Zhiru Zhang
2021	J	`jnl`	Guest Editors' Introduction: Machine Intelligence at the Edge. IEEE Des. Test Luca Benini, Deming Chen, Jinjun Xiong, Zhiru Zhang
2021	—	`conf`	Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks. ASP-DAC Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, Yibo Lin
2021	A	`conf`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2021	J	`jnl`	PokeBNN: A Binary Pursuit of Lightweight Accuracy. CoRR Yichi Zhang, Zhiru Zhang, Lukasz Lew
2021	J	`jnl`	Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects. ACM Trans. Reconfigurable Technol. Syst. Yi-Hsiang Lai, Ecenur Ustun, Shaojie Xiang, Zhenman Fang, Hongbo Rong, Zhiru Zhang
2021	A*	`conf`	SPADE: A Spectral Method for Black-Box Adversarial Robustness Evaluation. ICML Wuxinlin Cheng, Chenhui Deng, Zhiqiang Zhao, Yaohui Cai, Zhiru Zhang, Zhuo Feng
2021	J	`jnl`	SPADE: A Spectral Method for Black-Box Adversarial Robustness Evaluation. CoRR Wuxinlin Cheng, Chenhui Deng, Zhiqiang Zhao, Yaohui Cai, Zhiru Zhang, Zhuo Feng
2021	B	`conf`	Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. FMCAD Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra
2021	J	`jnl`	Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. CoRR Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra
2020	A*	`conf`	A-QED Verification of Hardware Accelerators. DAC Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang, Clark W. Barrett, Subhasish Mitra
2020	A	`conf`	Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. ICCAD Ecenur Ustun, Chenhui Deng, Debjit Pal, Zhijing Li, Zhiru Zhang
2020	A*	`conf`	Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. DAC Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong
2020	A	`conf`	Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. FPGA Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong
2020	J	`jnl`	Dagger: Towards Efficient RPCs in Cloud Microservices With Near-Memory Reconfigurable NICs. IEEE Comput. Archit. Lett. Nikita Lazarev, Neil Adit, Shaojie Xiang, Zhiru Zhang, Christina Delimitrou
2020	J	`jnl`	Dagger: Towards Efficient RPCs in Cloud Microservices with Near-Memory Reconfigurable NICs. CoRR Nikita Lazarev, Neil Adit, Shaojie Xiang, Zhiru Zhang, Christina Delimitrou
2020	J	`jnl`	FeatGraph: A Flexible and Efficient Backend for Graph Neural Network Systems. CoRR Yuwei Hu, Zihao Ye, Minjie Wang, Jiali Yu, Da Zheng, Mu Li, Zheng Zhang, Zhiru Zhang, Yida Wang
2020	A	`conf`	FeatGraph: a flexible and efficient backend for graph neural network systems. SC Yuwei Hu, Zihao Ye, Minjie Wang, Jiali Yu, Da Zheng, Mu Li, Zheng Zhang, Zhiru Zhang, Yida Wang
2020	J	`jnl`	FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations. CoRR Yichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen, Zhiru Zhang
2020	A*	`conf`	GraphZoom: A Multi-level Spectral Approach for Accurate and Scalable Graph Embedding. ICLR Chenhui Deng, Zhiqiang Zhao, Yongyu Wang, Zhiru Zhang, Zhuo Feng
2020	J	`jnl`	GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning. CoRR Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
2020	J	`jnl`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2020	A*	`conf`	MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product. MICRO Nitish Kumar Srivastava, Hanchen Jin, Jie Liu, David H. Albonesi, Zhiru Zhang
2020	J	`jnl`	MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration. CoRR Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
2020	A*	`conf`	Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. ICLR Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang
2020	J	`jnl`	Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. CoRR Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang
2020	J	`jnl`	Predictable Accelerator Design with Time-Sensitive Affine Types. CoRR Rachit Nigam, Sachille Atapattu, Samuel Thomas, Zhijing Li, Theodore Bauer, Yuwei Ye, Apurva Koti, Adrian Sampson, Zhiru Zhang
2020	A*	`conf`	Predictable accelerator design with time-sensitive affine types. PLDI Rachit Nigam, Sachille Atapattu, Samuel Thomas, Zhijing Li, Theodore Bauer, Yuwei Ye, Apurva Koti, Adrian Sampson, Zhiru Zhang
2020	A	`conf`	SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey
2020	A*	`conf`	Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations. HPCA Nitish Kumar Srivastava, Hanchen Jin, Shaden Smith, Hongbo Rong, David H. Albonesi, Zhiru Zhang
2019	—	`conf`	A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski
2019	A*	`conf`	Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating. MICRO Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh
2019	A*	`conf`	Building Efficient Deep Neural Networks With Unitary Group Convolutions. CVPR Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang
2019	A*	`conf`	Channel Gating Neural Networks. NeurIPS Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh
2019	A*	`conf`	Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES. DAC Zhenghong Jiang, Hanchen Jin, G. Edward Suh, Zhiru Zhang
2019	J	`jnl`	GraphZoom: A multi-level spectral approach for accurate and scalable graph embedding. CoRR Chenhui Deng, Zhiqiang Zhao, Yongyu Wang, Zhiru Zhang, Zhuo Feng
2019	A	`conf`	HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang
2019	A*	`conf`	Improving Neural Network Quantization without Retraining using Outlier Channel Splitting. ICML Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang
2019	J	`jnl`	Improving Neural Network Quantization without Retraining using Outlier Channel Splitting. CoRR Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang
2019	A*	`conf`	Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning. DAC Steve Dai, Zhiru Zhang
2019	Misc	`conf`	LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure. FCCM Ecenur Ustun, Shaojie Xiang, Jinny Gui, Cunxi Yu, Zhiru Zhang
2019	J	`jnl`	Overwrite Quantization: Opportunistic Outlier Handling for Neural Network Accelerators. CoRR Ritchie Zhao, Christopher De Sa, Zhiru Zhang
2019	J	`jnl`	PIMap: A Flexible Framework for Improving LUT-Based Technology Mapping via Parallelized Iterative Optimization. ACM Trans. Reconfigurable Technol. Syst. Gai Liu, Zhiru Zhang
2019	A*	`conf`	PRIMAL: Power Inference using Machine Learning. DAC Yuan Zhou, Haoxing Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang
2019	A*	`conf`	Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets. DAC Cunxi Yu, Zhiru Zhang
2019	J	`jnl`	Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets. CoRR Cunxi Yu, Zhiru Zhang
2019	A*	`conf`	Rapid Generation of High-Qality RISC-V Processors from Functional Instruction Set Specifications. DAC Gai Liu, Joseph Primmer, Zhiru Zhang
2019	Misc	`conf`	T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations. FCCM Nitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, David H. Albonesi, Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Adam Herr, Christopher J. Hughes, Timothy G. Mattson, Pradeep Dubey
2018	A	`conf`	A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation. FPGA Steve Dai, Gai Liu, Zhiru Zhang
2018	J	`jnl`	Building Efficient Deep Neural Networks with Unitary Group Convolutions. CoRR Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang
2018	J	`jnl`	Channel Gating Neural Networks. CoRR Weizhe Hua, Christopher De Sa, Zhiru Zhang, G. Edward Suh
2018	A	`conf`	DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only). FPGA Gai Liu, Ecenur Ustun, Shaojie Xiang, Chang Xu, Guojie Luo, Zhiru Zhang
2018	Misc	`conf`	Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. FCCM Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang
2018	A	`conf`	High-level synthesis with timing-sensitive information flow enforcement. ICCAD Zhenghong Jiang, Steve Dai, G. Edward Suh, Zhiru Zhang
2018	A*	`conf`	Reverse engineering convolutional neural networks through side-channel information leaks. DAC Weizhe Hua, Zhiru Zhang, G. Edward Suh
2018	A	`conf`	Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. FPGA Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang
2018	J	`jnl`	The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. IEEE Micro Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, Michael B. Taylor
2017	A	`conf`	A New Approach to Automatic Memory Banking using Trace-Based Address Mining. FPGA Yuan Zhou, Khalid Musa Al-Hawaj, Zhiru Zhang
2017	A	`conf`	A Parallel Bandit-Based Approach for Autotuning FPGA Compilation. FPGA Chang Xu, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, Zhiru Zhang
2017	A	`conf`	A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping. FPGA Gai Liu, Zhiru Zhang
2017	A	`conf`	Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs. FPGA Ritchie Zhao, Weinan Song, Wentao Zhang, Tianwei Xing, Jeng-Hau Lin, Mani B. Srivastava, Rajesh Gupta, Zhiru Zhang
2017	A	`conf`	Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. FPGA Nitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang
2017	J	`jnl`	Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gai Liu, Mingxing Tan, Steve Dai, Ritchie Zhao, Zhiru Zhang
2017	—	`conf`	Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration. CVPR Workshops Jeng-Hau Lin, Tianwei Xing, Ritchie Zhao, Zhiru Zhang, Mani B. Srivastava, Zhuowen Tu, Rajesh K. Gupta
2017	J	`jnl`	Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration. CoRR Jeng-Hau Lin, Tianwei Xing, Ritchie Zhao, Zhiru Zhang, Mani B. Srivastava, Zhuowen Tu, Rajesh K. Gupta
2017	A	`conf`	Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. FPGA Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang
2017	Misc	`conf`	Enabling adaptive loop pipelining in high-level synthesis. ACSSC Steve Dai, Gai Liu, Ritchie Zhao, Zhiru Zhang
2017	Misc	`conf`	FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron Collider. FCCM Edward Bartz, Jorge Chaves, Yuri Gershtein, Eva Halkiadakis, Michael D. Hildreth, Savvas Kyriacou, Kevin Lannon, Anthony Lefeld, Anders Ryd, Louise Skinnari, Robert Stone, Charles Strohman, Zhengcheng Tao, Brian Winer, Peter Wittich, Zhiru Zhang, Margaret Zientek
2017	A	`conf`	Statistically certified approximate logic synthesis. ICCAD Gai Liu, Zhiru Zhang
2016	—	`conf`	Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling. ICCPS Abhinandan Majumdar, Zhiru Zhang, David H. Albonesi
2016	A*	`conf`	Improving high-level synthesis with decoupled data structure optimization. DAC Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang
2016	J	`jnl`	Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs. IET Cyper-Phys. Syst.: Theory & Appl. Deming Chen, Jason Cong, Swathi T. Gurumani, Wen-mei W. Hwu, Kyle Rupnow, Zhiru Zhang
2015	A*	`conf`	A reconfigurable analog substrate for highly efficient maximum flow computation. DAC Gai Liu, Zhiru Zhang
2015	A*	`conf`	Area-efficient pipelining for FPGA-targeted high-level synthesis. DAC Ritchie Zhao, Mingxing Tan, Steve Dai, Zhiru Zhang
2015	A	`conf`	DA Systemization of Knowledge: A Catalog of Prior Forward-Looking Initiatives. ICCAD Farinaz Koushanfar, Azalia Mirhoseini, Gang Qu, Zhiru Zhang
2015	A	`conf`	ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests. ICCAD Mingxing Tan, Gai Liu, Ritchie Zhao, Steve Dai, Zhiru Zhang
2015	J	`jnl`	High-level Synthesis for Low-power Design. IPSJ Trans. Syst. LSI Des. Methodol. Zhiru Zhang, Deming Chen, Steve Dai, Keith A. Campbell
2015	A	`conf`	Mapping-Aware Constrained Scheduling for LUT-Based FPGAs. FPGA Mingxing Tan, Steve Dai, Udit Gupta, Zhiru Zhang
2014	A*	`conf`	Architectural Specialization for Inter-Iteration Loop Dependence Patterns. MICRO Shreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang, Christopher Batten
2014	A	`conf`	CASA: correlation-aware speculative adders. ISLPED Gai Liu, Ye Tao, Mingxing Tan, Zhiru Zhang
2014	A*	`conf`	Flushing-Enabled Loop Pipelining for High-Level Synthesis. DAC Steve Dai, Mingxing Tan, Kecheng Hao, Zhiru Zhang
2014	A	`conf`	Multithreaded pipeline synthesis for data-parallel kernels. ICCAD Mingxing Tan, Bin Liu, Steve Dai, Zhiru Zhang
2013	A	`conf`	SDC-based modulo scheduling for pipeline synthesis. ICCAD Zhiru Zhang, Bin Liu
2012	J	`jnl`	ESL Design Methodology. J. Electr. Comput. Eng. Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang
2011	J	`jnl`	High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang
2010	J	`jnl`	Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Bin Liu, Rupak Majumdar, Zhiru Zhang
2010	A	`conf`	Bit-level optimization for high-level synthesis and FPGA-based acceleration. FPGA Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong
2010	—	`conf`	Image classification with spectral and texture features based on SVM. Geoinformatics Fen Chen, Zhiru Zhang, Dongmei Yan
2009	A	`conf`	Behavior-level observability don't-cares and application to low-power behavioral synthesis. ISLPED Jason Cong, Bin Liu, Zhiru Zhang
2009	Misc	`conf`	Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. FCCM Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Zhiru Zhang, Sheng Zhou, Yi Zou
2009	A	`conf`	Revisiting bitwidth optimizations. FPGA Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou
2009	A	`conf`	Scheduling with soft constraints. ICCAD Jason Cong, Bin Liu, Zhiru Zhang
2008	—	`conf`	Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. ASP-DAC Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang
2008	—	`conf`	Scheduling with integer time budgeting for low-power optimization. ASP-DAC Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong
2007	—	`conf`	High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. ASP-DAC Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang
2006	A*	`conf`	An efficient and versatile scheduling algorithm based on SDC formulation. DAC Jason Cong, Zhiru Zhang
2006	J	`jnl`	Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. IEEE Trans. Very Large Scale Integr. Syst. Jason Cong, Guoling Han, Zhiru Zhang
2006	A*	`conf`	Behavior and communication co-optimization for systems with sequential communication media. DAC Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
2006	—	`conf`	Platform-Based Behavior-Level and System-Level Synthesis. SoCC Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
2005	A	`conf`	Architecture and compilation for data bandwidth improvement in configurable embedded processors. ICCAD Jason Cong, Guoling Han, Zhiru Zhang
2005	—	`conf`	Bitwidth-aware scheduling and binding in high-level synthesis. ASP-DAC Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng
2005	A	`conf`	Instruction set extension with shadow registers for configurable processors. FPGA Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang
2004	A	`conf`	Application-specific instruction generation for configurable processor architectures. FPGA Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang
2004	J	`jnl`	Architecture and synthesis for on-chip multicycle communication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
2004	A*	`conf`	Architecture-level synthesis for automatic interconnect pipelining. DAC Jason Cong, Yiping Fan, Zhiru Zhang
2003	A	`conf`	Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. ICCAD Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
2003	—	`conf`	Architecture and synthesis for multi-cycle communication. ISPD Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
2003	Misc	`conf`	Architecture and synthesis for multi-cycle on-chip communication. CODES+ISSS Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
2003	A	`conf`	Gradual Relaxation Techniques with Applications to Behavioral Synthesis. ICCAD Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong