Zhiqiang Cui

16 papers C 5Journal 8Unranked 3

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Maintenance Spare Parts Prediction Based on Multilevel Migration Learning CNN-ISE-Attention-BiLSTM. IEEE Access Zhiqiang Cui, Hongli Jia, Qi Gao, Haowen Song
2023	J	`jnl`	The Use of Regional Data Assimilation to Improve Numerical Simulations of Diurnal Characteristics of Precipitation during an Active Madden-Julian Oscillation Event over the Maritime Continent. Remote. Sens. Zhiqiang Cui, Zhaoxia Pu
2014	C	`conf`	Multilevel error correction scheme for MLC flash memory. ISCAS Zhiqiang Cui, Zhongfeng Wang, Xinming Huang
2012	J	`jnl`	Reduced-Complexity Column-Layered Decoding and Implementation for LDPC Codes CoRR Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang
2011	J	`jnl`	Reduced-complexity column-layered decoding and implementation for LDPC codes. IET Commun. Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang
2009	J	`jnl`	High-Throughput Layered LDPC Decoding Architecture. IEEE Trans. Very Large Scale Integr. Syst. Zhiqiang Cui, Zhongfeng Wang, Youjian Liu
2009	C	`conf`	Towards an Optimal Trade-off of Viterbi Decoder Design. ISCAS Jinjin He, Zhongfeng Wang, Zhiqiang Cui, Li Li
2008	—	`conf`	Efficient decoder design for high-throughput LDPC decoding. APCCAS Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang, Qingwei Jia
2008	—	`conf`	Extended layered decoding of LDPC codes. ACM Great Lakes Symposium on VLSI Zhiqiang Cui, Zhongfeng Wang
2008	J	`jnl`	Improved low-complexity low-density parity-check decoding. IET Commun. Zhiqiang Cui, Zhongfeng Wang
2007	J	`jnl`	A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. Zhongfeng Wang, Zhiqiang Cui
2007	C	`conf`	Efficient Message Passing Architecture for High Throughput LDPC Decoder. ISCAS Zhiqiang Cui, Zhongfeng Wang
2007	J	`jnl`	Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. Zhongfeng Wang, Zhiqiang Cui
2007	—	`conf`	Studies on Practical Low Complexity Decoding of Low-Density Parity-Check Codes. SiPS Zhiqiang Cui, Zhongfeng Wang
2006	C	`conf`	A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. ISCAS Zhiqiang Cui, Zhongfeng Wang
2006	C	`conf`	Area-efficient parallel decoder architecture for high rate QC-LDPC codes. ISCAS Zhiqiang Cui, Zhongfeng Wang