Zhiheng Yue

38 papers A* 10Journal 15Unranked 13
YearRankTypeTitle / Venue / Authors
2026 — conf
2.9 A 0.24mJ/Frame Quadratic Interpolation 4DGS Processor with Recursive Computation Reuse and Tree-Based Parallel-Rendering.
ISSCC
Xiaolong Yang, Yang Wang, Wende Xu, Yubin Qin, Huanyu Wang, Ruiqi Guo, Zhiheng Yue, Jiangyuan Gu, Shaojun Wei, Yang Hu, Shouyi Yin
2026 — conf
A 28nm 47.3TFLOPs/W 894mJ/Inference Visual Autoregressive Accelerator with Differential-Amplifier Speculation and Chain-Reaction-Like Parallel Generation.
ISSCC
Zhiheng Yue, Xujiang Xiang, Jiamu Fu, Shaojun Wei, Yang Wang, Yang Hu, Shouyi Yin
2026 — conf
A 28nm Speculative-Decoding LLM Processor Achieving 105-to-685µs/Token Latency for Billion-Parameter Models.
ISSCC
Yang Wang, Huanyu Wang, Jiaxin Yang, Yutong Su, Ruiqi Guo, Zhiheng Yue, Jiangyuan Gu, Shaojun Wei, Yang Hu, Shouyi Yin
2026 J jnl
Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling.
IEEE Trans. Computers
Huizheng Wang, Taiquan Wei, Hongbin Wang, Zichuan Wang, Xinru Tang, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2026 A* conf
HR-DCIM: High-Reliability Floating-Point Digital CIM Architecture With Unified Low-Cost Iterative Error Correction.
HPCA
Zhen He, Yiqi Wang, Zhiheng Yue, Zihan Wu, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2026 A* conf
PADE: A Predictor-Free Sparse Attention Accelerator via Unified Execution and Stage Fusion.
HPCA
Huizheng Wang, Hongbin Wang, Zichuan Wang, Zhiheng Yue, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2026 A* conf
ReThermal: Co-Design of Thermal-Aware Static and Dynamic Scheduling for LLM Training on Liquid-Cooled Wafer-Scale Chips.
HPCA
Chengran Li, Huizheng Wang, Jiaxin Liu, Jingyao Liu, Zhiheng Yue, Xia Li, Shenfei Jiang, Jinyi Deng, Yang Hu, Shouyi Yin
2025 — conf
14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <
ISSCC
Zhiheng Yue, Xujiang Xiang, Yang Wang, Ruiqi Guo, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2025 A* conf
3D-PATH: A Hierarchy LUT Processing-in-memory Accelerator with Thermal-aware Hybrid Bonding Integration.
MICRO
Zhiheng Yue, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025 J jnl
A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array.
IEEE J. Solid State Circuits
Ruiqi Guo, Zhiheng Yue, Yang Wang, Hao Li, Te Hu, Yabing Wang, Hao Sun, Jeng-Long Hsu, Yaojun Zhang, Bonan Yan, Leibo Liu, Ru Huang, Shaojun Wei, Shouyi Yin
2025 J jnl
An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications.
IEEE J. Solid State Circuits
Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2025 J jnl
BETA: A Bit-Grained Transformer Attention Accelerator With Efficient Early Termination.
IEEE Trans. Circuits Syst. II Express Briefs
Huizheng Wang, Hongbin Wang, Zhiheng Yue, Jingyao Liu, Taiquan Wei, Shaojun Wei, Yang Hu, Shouyi Yin
2025 J jnl
CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction.
IEEE J. Solid State Circuits
Zhiheng Yue, Yang Wang, Huizheng Wang, Ruiqi Guo, Fengbin Tu, Jianxun Yang, Shaojun Wei, Yang Hu, Shouyi Yin
2025 J jnl
Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling.
CoRR
Huizheng Wang, Taiquan Wei, Hongbin Wang, Zichuan Wang, Xinru Tang, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2025 J jnl
Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xujiang Xiang, Zhiheng Yue, Xiaolong Zhang, Shaojun Wei, Yang Hu, Shouyi Yin
2025 A* conf
MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness.
MICRO
Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025 J jnl
MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness.
CoRR
Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025 J jnl
PADE: A Predictor-Free Sparse Attention Accelerator via Unified Execution and Stage Fusion.
CoRR
Huizheng Wang, Hongbin Wang, Zichuan Wang, Zhiheng Yue, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2024 — conf
15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch.
ISSCC
Zhiheng Yue, Xujiang Xiang, Fengbin Tu, Yang Wang, Yiming Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2024 — conf
20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models.
ISSCC
Ruiqi Guo, Lei Wang, Xiaofeng Chen, Hao Sun, Zhiheng Yue, Yubin Qin, Huiming Han, Yang Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin
2024 — conf
34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications.
ISSCC
Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2024 — conf
A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating.
VLSI Technology and Circuits
Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2024 — conf
A 28nm 118.26TOPS/W Multi-Dimensional Fault-Tolerant Al Processor Enabling Voltage-Frequency Scaling Below Point-of-First-Failure.
A-SSCC
Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2024 A* conf
CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm.
DAC
Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2024 A* conf
Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization.
DAC
Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu, Shouyi Yin
2024 J jnl
Efficient Orchestrated AI Workflows Execution on Scale-Out Spatial Architecture.
IEEE Trans. Circuits Syst. Artif. Intell.
Jinyi Deng, Xinru Tang, Zhiheng Yue, Guangyang Lu, Qize Yang, Jiahao Zhang, Jinxi Li, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2024 J jnl
Efficient Orchestrated AI Workflows Execution on Scale-out Spatial Architecture.
CoRR
Jinyi Deng, Xinru Tang, Zhiheng Yue, Guangyang Lu, Qize Yang, Jiahao Zhang, Jinxi Li, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2024 A* conf
Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture.
ISCA
Zhiheng Yue, Huizheng Wang, Jiahao Fang, Jinyi Deng, Guangyang Lu, Fengbin Tu, Ruiqi Guo, Yuxuan Li, Yubin Qin, Yang Wang, Chao Li, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2024 A* conf
SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling.
MICRO
Huizheng Wang, Jiahao Fang, Xinru Tang, Zhiheng Yue, Jinxi Li, Yubin Qin, Sihan Guan, Qinze Yang, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2024 J jnl
SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling.
CoRR
Huizheng Wang, Jiahao Fang, Xinru Tang, Zhiheng Yue, Jinxi Li, Yubin Qin, Sihan Guan, Qize Yang, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2023 — conf
A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing.
VLSI Technology and Circuits
Yang Wang, Yubin Qin, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023 — conf
A Systolic Computing-in-Memory Array based Accelerator with Predictive Early Activation for Spatiotemporal Convolutions.
AICAS
Xiaofeng Chen, Ruiqi Guo, Zhiheng Yue, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin
2023 — conf
CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction.
ISSCC
Zhiheng Yue, Yang Wang, Huizheng Wang, Yabing Wang, Ruiqi Guo, Limei Tang, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023 J jnl
STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Weiwei Wu, Fengbin Tu, Mengqi Niu, Zhiheng Yue, Leibo Liu, Shaojun Wei, Xiangyu Li, Yang Hu, Shouyi Yin
2023 J jnl
TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization.
IEEE J. Solid State Circuits
Ruiqi Guo, Zhiheng Yue, Xin Si, Hao Li, Te Hu, Limei Tang, Yabing Wang, Hao Sun, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin
2022 J jnl
BR-CIM: An Efficient Binary Representation Computation-In-Memory Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhiheng Yue, Yabing Wang, Yubin Qin, Leibo Liu, Shaojun Wei, Shouyi Yin
2022 A* conf
MC-CIM: a reconfigurable computation-in-memory for efficient stereo matching cost computation.
DAC
Zhiheng Yue, Yabing Wang, Leibo Liu, Shaojun Wei, Shouyi Yin
2021 — conf
15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization.
ISSCC
Ruiqi Guo, Zhiheng Yue, Xin Si, Te Hu, Hao Li, Limei Tang, Yabing Wang, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin