Zhigang Mao - RankMe

148 papers A* 6A 9B 6C 10Journal 65Unranked 52

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A power-efficient multiplier with fine-grained power management. Microelectron. J. Tong Li, Honglan Jiang, Qin Wang, Jianfei Jiang, Zhigang Mao
2026	J	`jnl`	Leveraging Tensor Dataflow for Improved Thermal Performance on 3D-Stacked SRAM Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pengyu Liu, Liyan Chen, Zelong Yuan, Yingkun Liu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2026	J	`jnl`	Signal integrity-aware multi-path design workflow for ultra-large-scale three-dimensional chips: A logic-on-memory stacking case study. Microelectron. J. Ang Li, Jianfei Jiang, Naifeng Jing, Yanan Sun, Zhigang Mao, Qin Wang
2026	—	`conf`	Viper: An ILP-Based Vectorization Framework for Fully Homomorphic Encryption. ASP-DAC Weidong Yang, Xinmo Li, Xiangmin Guo, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2025	J	`jnl`	A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. IEEE Trans. Very Large Scale Integr. Syst. Zizheng Dong, Shuaipeng Li, Weijia Zhu, Ang Li, Qin Wang, Naifeng Jing, Weiguang Sheng, Jianfei Jiang, Zhigang Mao
2025	A	`conf`	A Low-Power Mixed-Precision Integrated Multiply-Accumulate Architecture for Quantized Deep Neural Networks. DATE Xiaolu Hu, Xinkuang Geng, Zhigang Mao, Jie Han, Honglan Jiang
2025	J	`jnl`	A novel method for screening malignant hematological diseases by constructing an optimal machine learning model based on blood cell parameters. BMC Medical Informatics Decis. Mak. Dehua Sun, Wei Chen, Jun He, Yongjian He, Haoqin Jiang, Hong Jiang, Dandan Liu, Lu Li, Min Liu, Zhigang Mao, Chenxue Qu, Linlin Qu, Ziyong Sun, Jianbiao Wang, Wenjing Wu, Xuefeng Wang, Wei Xu, Ying Xing, Chi Zhang, Jingxian Zhang, Lei Zheng, Shihong Zhang, Bo Ye, Ming Guan
2025	A*	`conf`	AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing. HPCA Liyan Chen, Dongxu Lyu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025	A*	`conf`	AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory. DAC Liyan Chen, Dongxu Lyu, Zhenyu Li, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025	J	`jnl`	Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Liyan Chen, Pengyu Liu, Dongxu Lyu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025	A*	`conf`	EPIC: Error PredIction and Correction for Power-Efficient Voltage Underscaling Multiply-Accumulate Unit. DAC Tongjing Wu, Xiaolu Hu, Tong Li, Siting Liu, Hui Wang, Weifeng He, Zhigang Mao, Honglan Jiang
2025	J	`jnl`	Efficient Extraction and Packing Modules for Posit Multipliers. IEEE Trans. Circuits Syst. II Express Briefs Tong Li, Honglan Jiang, Zhou Wang, Qin Wang, Jianfei Jiang, Zhigang Mao
2025	A	`conf`	HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. DATE Weidong Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2025	J	`jnl`	L3: DIMM-PIM Integrated Architecture and Coordination for Scalable Long-Context LLM Inference. CoRR Qingyuan Liu, Liyan Chen, Yanning Yang, Haocheng Wang, Dong Du, Zhigang Mao, Naifeng Jing, Yubin Xia, Haibo Chen
2025	J	`jnl`	Low-Power Multiplier Designs by Leveraging Correlations of 2$\times$×2 Encoded Partial Products. IEEE Trans. Computers Ao liu, Siting Liu, Hui Wang, Qin Wang, Fabrizio Lombardi, Zhigang Mao, Honglan Jiang
2025	J	`jnl`	MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Honglan Jiang, Zhigang Mao, Qin Wang
2025	—	`conf`	MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing. ASP-DAC Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024	J	`jnl`	3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zihan Zhang, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024	J	`jnl`	A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pengyu Liu, Ang Li, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024	J	`jnl`	A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance. Expert Syst. Appl. Kunyue Li, Zhengji Zhao, Qixuan Cai, Qin Wang, Naifeng Jing, Zhigang Mao, Jianfei Jiang
2024	J	`jnl`	An Architectural Error Metric for CNN-Oriented Approximate Multipliers. CoRR Ao liu, Jie Han, Qin Wang, Zhigang Mao, Honglan Jiang
2024	B	`conf`	Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture. ASPDAC Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024	J	`jnl`	DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024	J	`jnl`	RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Weidong Yang, Yuqing Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2024	B	`conf`	SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration. ASPDAC Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2023	—	`conf`	A Hierarchical Communication Algorithm for Distributed Deep Learning Training. MWSCAS Jiayu Zhang, Shaojun Cheng, Feng Dong, Ke Chen, Yong Qiao, Zhigang Mao, Jianfei Jiang
2023	J	`jnl`	A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen Yin, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao
2023	—	`conf`	An Efficient near-Bank Processing Architecture for Personalized Recommendation System. ASP-DAC Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng
2023	J	`jnl`	BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars. IEEE Trans. Circuits Syst. I Regul. Pap. Yanan Sun, Zhi Li, Weiyi Liu, Weifeng He, Qin Wang, Zhigang Mao
2023	J	`jnl`	CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuxuan Qin, Chuxiong Lin, Weifeng He, Yanan Sun, Zhigang Mao, Mingoo Seok
2023	—	`conf`	MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5. ASICON Xiaoyan Li, Zizheng Dong, Shuaipeng Li, Sai Gao, Jianfei Jiang, Guanghui He, Zhigang Mao
2023	B	`conf`	Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. FPL Pengyu Liu, Zihan Zhang, Chen Yin, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2023	—	`conf`	RTMDet-R2: An Improved Real-Time Rotated Object Detector. PRCV (12) Haifeng Xiang, Naifeng Jing, Jianfei Jiang, Hongbo Guo, Weiguang Sheng, Zhigang Mao, Qin Wang
2022	J	`jnl`	A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taozhong Li, Naifeng Jing, Zhigang Mao, Yiran Chen
2022	J	`jnl`	A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. IEEE Geosci. Remote. Sens. Lett. Guochao Deng, Qin Wang, Jianfei Jiang, Qirun Hong, Naifeng Jing, Weiguang Sheng, Zhigang Mao
2022	J	`jnl`	A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator. ACM Trans. Design Autom. Electr. Syst. Taozhong Li, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao, Yiran Chen
2022	J	`jnl`	A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zihan Zhang, Jianfei Jiang, Yongxin Zhu, Qin Wang, Zhigang Mao, Naifeng Jing
2022	J	`jnl`	An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Shengzhao Li, Qin Wang, Jianfei Jiang, Weiguang Sheng, Naifeng Jing, Zhigang Mao
2022	J	`jnl`	MSLM-RF: A Spatial Feature Enhanced Random Forest for On-Board Hyperspectral Image Classification. IEEE Trans. Geosci. Remote. Sens. Shuai Yuan, Yanan Sun, Weifeng He, Qianrong Gu, Shi Xu, Zhigang Mao, Shikui Tu
2022	J	`jnl`	Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits. IEEE Access Linzhe Li, Liyi Xiao, He Liu, Zhigang Mao
2021	J	`jnl`	A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. IEEE Trans. Very Large Scale Integr. Syst. Zhuojun Liang, Dongxu Lv, Chao Cui, Hai-Bao Chen, Weifeng He, Weiguang Sheng, Naifeng Jing, Zhigang Mao, Guanghui He
2021	—	`conf`	A Mapping Method for Reconfigurable Array based on Decoupled DataFlow. BigDataSecurity Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, Naifeng Jing
2021	J	`jnl`	Automatic Detection for Acromegaly Using Hand Photographs: A Deep-Learning Approach. IEEE Access Chengbin Duan, Wenli Chen, Shun Yao, Zhigang Mao, Zongming Wang, Bin Hu, Haosen Jiao, Dimin Zhu, Yonghong Zhu, Haijun Wang
2021	A*	`conf`	CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement. DAC Chuxiong Lin, Weifeng He, Yanan Sun, Zhigang Mao, Mingoo Seok
2021	J	`jnl`	MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip. IEEE J. Solid State Circuits Chuxiong Lin, Weifeng He, Yanan Sun, Bingxi Pei, Pavan Kumar Chundi, Zhigang Mao, Mingoo Seok
2021	A	`conf`	Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. DATE Yuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng
2021	A	`conf`	Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. DATE Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing
2020	—	`conf`	25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip. ISSCC Chuxiong Lin, Weifeng He, Yanan Sun, Bingxi Pei, Zhigang Mao, Mingoo Seok
2020	—	`conf`	Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. ACM Great Lakes Symposium on VLSI Zihan Zhang, Taozhong Li, Ning Guan, Qin Wang, Guanghui He, Weiguang Sheng, Zhigang Mao, Naifeng Jing
2020	J	`jnl`	Evaluating the influences of harvesting activity and eutrophication on loss of aquatic vegetations in Taihu Lake, China. Int. J. Appl. Earth Obs. Geoinformation Juhua Luo, Ruiliang Pu, Hongtao Duan, Ronghua Ma, Zhigang Mao, Yuan Zeng, Linsheng Huang, Qitao Xiao
2020	J	`jnl`	Mapping Long-Term Spatiotemporal Dynamics of Pen Aquaculture in a Shallow Lake: Less Aquaculture Coming along Better Water Quality. Remote. Sens. Juhua Luo, Ruiliang Pu, Ronghua Ma, Xiaolong Wang, Xijun Lai, Zhigang Mao, Li Zhang, Zhaoliang Peng, Zhe Sun
2020	J	`jnl`	Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density. IEEE Trans. Circuits Syst. I Regul. Pap. Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
2020	J	`jnl`	Priority Branches for Ship Detection in Optical Remote Sensing Images. Remote. Sens. Yijia Zhang, Weiguang Sheng, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao
2020	J	`jnl`	Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling. IEEE Trans. Parallel Distributed Syst. Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Wenzhi Yin, Pengfei Ye, Jinchao Li, Zhigang Mao
2019	—	`conf`	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency. NANOARCH Yongjie Lu, Yanan Sun, Weifeng He, Zhigang Mao
2019	J	`jnl`	A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. ACM Trans. Design Autom. Electr. Syst. Taozhong Li, Qin Wang, Yongxin Zhu, Jianfei Jiang, Guanghui He, Jing Jin, Zhigang Mao, Naifeng Jing
2019	—	`conf`	Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections. ASICON Jiachen Jiang, Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun
2019	J	`jnl`	Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. IEEE Trans. Circuits Syst. II Express Briefs Yanan Sun, Jiawei Gu, Weifeng He, Qin Wang, Naifeng Jing, Zhigang Mao, Weikang Qian, Li Jiang
2019	—	`conf`	Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes. ICEIC Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
2019	—	`conf`	Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit. ASICON Linzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao
2019	B	`conf`	mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator. ISPASS Zhongyuan Zhao, Hyoukjun Kwon, Sachit Kuhar, Weiguang Sheng, Zhigang Mao, Tushar Krishna
2018	J	`jnl`	Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications. IEEE Trans. Very Large Scale Integr. Syst. Jing Guo, Lei Zhu, Yu Sun, Huiliang Cao, Hai Huang, Tianqi Wang, Chunhua Qi, Rongsheng Zhang, Xuebing Cao, Liyi Xiao, Zhigang Mao
2018	—	`conf`	MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. ReConFig Shuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao
2018	A	`conf`	Optimizing the data placement and transformation for multi-bank CGRA computing system. DATE Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao
2017	J	`jnl`	A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras. Integr. Wei Jin, Guanghui He, Weifeng He, Zhigang Mao
2017	A	`conf`	A static-placement, dynamic-issue framework for CGRA loop accelerator. DATE Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li
2017	J	`jnl`	Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC. Integr. Qin Wang, Zhenyang Chen, Jianfei Jiang, Zheng Guo, Zhigang Mao
2017	J	`jnl`	In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations. IEEE Trans. Very Large Scale Integr. Syst. Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
2017	—	`conf`	Low redundancy matrix-based codes for adjacent error correction with parity sharing. ISQED Shanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, Zhigang Mao
2017	—	`conf`	Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. ASICON Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
2017	J	`jnl`	Near- and Sub-V IEEE J. Solid State Circuits Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
2017	J	`jnl`	Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. Jing Guo, Lei Zhu, Wenyi Liu, Hai Huang, Shanshan Liu, Tianqi Wang, Liyi Xiao, Zhigang Mao
2017	—	`conf`	Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability. ASP-DAC Shanshan Liu, Liyi Xiao, Xuebing Cao, Zhigang Mao
2017	J	`jnl`	Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic. Microelectron. J. Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun
2016	—	`conf`	A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines. A-SSCC Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
2016	J	`jnl`	Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding. IEICE Electron. Express Liang Hong, Wei-Feng He, Guanghui He, Zhigang Mao
2016	J	`jnl`	Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. J. Circuits Syst. Comput. Jianfei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang, Weifeng He
2016	—	`conf`	Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. FPT Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao
2016	J	`jnl`	Extend orthogonal Latin square codes for 32-bit data protection in memory applications. Microelectron. Reliab. Shanshan Liu, Liyi Xiao, Zhigang Mao
2016	J	`jnl`	High performance parallel turbo decoder with configurable interleaving network for LTE application. Integr. Zhiting Yan, Guanghui He, Weifeng He, Shuaijie Wang, Zhigang Mao
2016	J	`jnl`	Parallel SER analysis for combinational and sequential standard cell circuits. Microelectron. J. Weiguang Sheng, Jianfei Jiang, Zhigang Mao
2015	—	`conf`	A contactless testing methodology for pre-bond interposer. MWSCAS Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao
2015	—	`conf`	A crosstalk avoidance scheme based on re-layout of signal TSV. ASICON Jiayi Hu, Qin Wang, Jianfei Jiang, Jing Xie, Zhigang Mao
2015	J	`jnl`	Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing. IEEE Trans. Circuits Syst. I Regul. Pap. Zhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jianfei Jiang, Zhigang Mao
2015	J	`jnl`	Design optimization for capacitive-resistively driven on-chip global interconnect. IEICE Electron. Express Jianfei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao
2015	—	`conf`	Fault Secure Encoder and Decoder Designs for Matrix Codes. CAD/Graphics Shanshan Liu, Liyi Xiao, Jing Guo, Zhigang Mao
2015	—	`conf`	Fault detection and redundancy design for TSVs in 3D ICs. ASICON Sai Hu, Qin Wang, Zheng Guo, Jing Xie, Zhigang Mao
2015	J	`jnl`	Improved Iterative Receiver for Co-channel Interference Suppression in MIMO-OFDM Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Zhiting Yan, Guanghui He, Weifeng He, Zhigang Mao
2015	C	`conf`	Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework. PRDC Weiguang Sheng, Zhongyuan Zhao, Zhigang Mao
2015	A	`conf`	Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. ICCAD Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao
2015	—	`conf`	Resource-saving compile flow for coarse-grained reconfigurable architectures. ReConFig Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao
2015	J	`jnl`	Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology. IEEE Trans. Reliab. Jing Guo, Liyi Xiao, Tianqi Wang, Shanshan Liu, Xu Wang, Zhigang Mao
2014	C	`conf`	Area and throughput efficient IDCT/IDST architecture for HEVC standard. ISCAS Ziyou Yao, Weifeng He, Liang Hong, Guanghui He, Zhigang Mao
2014	J	`jnl`	Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code. IEEE Trans. Very Large Scale Integr. Syst. Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao
2014	J	`jnl`	Improved Max-Log-MAP BICM-IDD receiver for MIMO systems. IEICE Electron. Express Zhiting Yan, Guanghui He, Xi Chen, Weifeng He, Zhigang Mao
2014	J	`jnl`	Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Jing Guo, Liyi Xiao, Zhigang Mao
2013	C	`conf`	A Block Cipher Circuit Design against Power Analysis. CIS Yuxiao Ling, Zheng Guo, Zhimin Zhang, Zhigang Mao, Zeleng Zhuang
2013	—	`conf`	A cost effective 2-D adaptive block size IDCT architecture for HEVC standard. MWSCAS Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao
2013	J	`jnl`	A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard. IEICE Electron. Express Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao
2013	—	`conf`	A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design. ASICON Zheng Tang, Jing Xie, Zhigang Mao
2013	—	`conf`	A soft-output parallel stack algorithm for MIMO detection. SiPS Zhi Yue, Guanghui He, Jiangpeng Li, Jun Ma, Zhigang Mao
2013	A*	`conf`	An energy-efficient and scalable eDRAM-based register file architecture for GPGPU. ISCA Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang
2013	—	`conf`	Analysis of electromechanical interface model for liquid floated micro-gyroscope. NEMS Mingyuan Ren, Xiaowei Liu, Wen Zuo, Zhigang Mao
2013	—	`conf`	Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor. ASICON Haopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao
2013	J	`jnl`	Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs. IEEE Micro Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao
2013	—	`conf`	TSVs-aware floorplanning for 3D integrated circuit. ASICON Jieliang Lu, Qin Wang, Jing Xie, Zhigang Mao
2012	—	`conf`	Contention and energy aware mapping for real-time applications on Network-on-Chip. ISOCC Bingjing Ge, Naifeng Jing, Weifeng He, Zhigang Mao
2012	—	`conf`	Novel O-GEHL Based Hyperblock Predictor for EDGE Architectures. NAS Pengfei Gou, Bing Yang, Mingyan Yu, Zhigang Mao
2012	—	`conf`	Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm. IPDPS Workshops Weiguang Sheng, Weifeng He, Jianfei Jiang, Zhigang Mao
2012	J	`jnl`	SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. ACM Trans. Design Autom. Electr. Syst. Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He
2011	C	`conf`	A 230mV 8-bit sub-threshold microprocessor for wireless sensor network. VLSI-SoC Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao
2011	C	`conf`	A general statistical estimation for application mapping in Network-on-Chip. VLSI-SoC Naifeng Jing, Weifeng He, Zhigang Mao
2011	—	`conf`	A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications. ASICON Jin Huang, Jing Xie, Zhigang Mao
2011	—	`conf`	A reconfigurable linear array processor architecture for data parallel and computation intensive applications. ASICON Yucheng Liu, Jing Xie, Zhigang Mao
2011	C	`conf`	A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor. ISCAS Li Xie, Weifeng He, Naifeng Jing, Zhigang Mao
2011	—	`conf`	An efficient 90nm technology-node GHz transceiver of on-chip global interconnect. ASICON Zaixiao Zheng, Zhigang Mao, Jianfei Jiang
2011	J	`jnl`	Companding schemes based on transforming signal statistics into trigonal distributions for PAPR reduction in OFDM systems. Int. J. Commun. Syst. Xin-chun Wu, Jinxiang Wang, Bin Zhou, Zhigang Mao, Zhiqiang Gao
2011	C	`conf`	Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems. ISCAS Yuliang Tao, Guanghui He, Weifeng He, Qin Wang, Jun Ma, Zhigang Mao
2011	—	`conf`	Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm. ASICON Yifan Zhou, Weiguang Sheng, Xie Liu, Weifeng He, Zhigang Mao
2011	A	`conf`	Fault modeling and characteristics of SRAM-based FPGAs (abstract only). FPGA Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He
2011	—	`conf`	Generalized interleaving network based on configurable QPP architecture for parallel turbo decoder. SiPS Shuaijie Wang, Jun Ma, Guanghui He, Zhigang Mao
2011	J	`jnl`	Low Complexity Time Domain Interleaved Partitioning Partial Transmit Sequence Scheme for Peak-to-Average Power Ratio Reduction of Orthogonal Frequency Division Multiplexing Systems. Wirel. Pers. Commun. Xin-chun Wu, Bin Zhou, Jinxiang Wang, Zhigang Mao
2011	A	`conf`	Mitigating FPGA interconnect soft errors by in-place LUT inversion. ICCAD Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He
2011	C	`conf`	On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system. VLSI-SoC Jing Xie, Huimin Xing, Zhigang Mao
2011	—	`conf`	Parallel SFSD MIMO detection with SOFT-HARD combination enumeration. SiPS Jianpeng Yu, Jun Ma, Zhigang Mao
2011	B	`conf`	Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. FPL Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He
2011	C	`conf`	Robust design of sub-threshold flip-flop cells for wireless sensor network. VLSI-SoC Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao
2010	—	`conf`	An efficient VLSI architecture for extended variable block sizes motion estimation. SoCC Weifeng He, Weiwei Chen, Zhigang Mao
2010	J	`jnl`	Conjugate Interleaved Partitioning PTS Scheme for PAPR Reduction of OFDM Signals. Circuits Syst. Signal Process. Xin-chun Wu, Jinxiang Wang, Zhigang Mao, Jianwei Zhang
2010	—	`conf`	Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array. SoCC Naifeng Jing, Weifeng He, Zhigang Mao
2010	J	`jnl`	Statistical estimation and evaluation for communication mapping in Network-on-Chip. Integr. Naifeng Jing, Weifeng He, Yongxin Zhu, Zhigang Mao
2009	A*	`conf`	Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. DAC Weiguang Sheng, Liyi Xiao, Zhigang Mao
2009	—	`conf`	Statistical Estimation for Total Communication Load in Application-Specific Network-on-Chip. ICESS Naifeng Jing, Zhigang Mao, Yongxin Zhu
2008	—	`conf`	A Hybrid Anti-Collision Algorithm for RFID with Enhanced Throughput and Reduced Memory Consumption. EUC (1) Majun Zheng, Jing Xie, Zhigang Mao, Yongxin Zhu
2008	—	`conf`	A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis. ICECS Weiguang Sheng, Liyi Xiao, Zhigang Mao
2008	—	`conf`	An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling. DELTA Weiguang Sheng, Liyi Xiao, Zhigang Mao
2008	C	`conf`	Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns. PRDC Weiguang Sheng, Liyi Xiao, Zhigang Mao
2007	—	`conf`	A Link-Load Balanced Low Energy Mapping and Routing for NoC. ICESS Wenbiao Zhou, Yan Zhang, Zhigang Mao
2006	J	`jnl`	A Restoration Algorithm for Images Contaminated by Impulse Noise. J. Comput. Res. Dev. Peng Liu, Yan Zhang, Zhigang Mao
2006	—	`conf`	Design and VLSI Architecture of a Channel Equalizer Based on Adaptive Modulation for IEEE 802.11a WLAN. APCCAS Wei Zhong, Zhigang Mao
2006	J	`jnl`	Efficient time-domain residual ISI cancellation for OFDM-based WLAN systems. IEEE Trans. Consumer Electron. Wei Zhong, Zhigang Mao
2006	—	`conf`	Pareto based Multi-objective Mapping IP Cores onto NoC Architectures. APCCAS Wenbiao Zhou, Yan Zhang, Zhigang Mao
2005	—	`conf`	Efficient frame-level pipelined array architecture for full-search block-matching motion estimation. ISCAS (3) Weifeng He, Yunlong Bi, Zhigang Mao
2004	B	`conf`	An adaptive motion estimation algorithm based on evolution strategies with correlated mutations. ICIP Hui Wang, Zhigang Mao
2004	—	`conf`	An adaptive motion estimation algorithm based on evolution strategies. ICASSP (3) Hui Wang, Zhigang Mao
2000	J	`jnl`	Implementation of Java Card Virtual Machine. J. Comput. Sci. Technol. Liu Songyan, Zhigang Mao, Yizheng Ye
1999	—	`conf`	A New Algorithm for Retiming-Based Partial Scan. Asian Test Symposium Zulan Huang, Yizheng Ye, Zhigang Mao
1998	—	`conf`	Test Pattern Generation for Column Compression Multiplier. Asian Test Symposium Pingying Zeng, Zhigang Mao, Yizheng Ye, Yuliang Deng