Zhichun Zhu - RankMe

34 papers A* 7A 3B 6C 1Journal 13Unranked 4

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Polling-Based Memory Interface. ACM Trans. Design Autom. Electr. Syst. Trung Le, Zhao Zhang, Zhichun Zhu
2023	J	`jnl`	Redundant Array of Independent Memory Devices. IEEE Comput. Archit. Lett. Peiyun Wu, Trung Le, Zhichun Zhu, Zhao Zhang
2022	—	`conf`	Dynamic Page Policy Using Perceptron Learning. MEMSYS Muhammad M. Rafique, Zhichun Zhu
2021	J	`jnl`	Memory-Side Prefetching Scheme Incorporating Dynamic Page Mode in 3D-Stacked DRAM. IEEE Trans. Parallel Distributed Syst. Muhammad M. Rafique, Zhichun Zhu
2021	C	`conf`	POMI: Polling-Based Memory Interface for Hybrid Memory System. ICCD Trung Le, Zhao Zhang, Zhichun Zhu
2020	B	`conf`	DeepSwapper: A Deep Learning Based Page Swap Management Scheme for Hybrid Memory Systems. PACT Majed Valad Beigi, Bahareh Pourshirazi, Gokhan Memik, Zhichun Zhu
2019	—	`conf`	FAPS-3D: feedback-directed adaptive page management scheme for 3D-stacked DRAM. MEMSYS Muhammad M. Rafique, Zhichun Zhu
2019	J	`jnl`	Writeback-Aware LLC Management for PCM-Based Main Memory Systems. ACM Trans. Design Autom. Electr. Syst. Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, Gokhan Memik
2018	B	`conf`	CAMPS: Conflict-Aware Memory-Side Prefetching Scheme for Hybrid Memory Cube. ICPP Muhammad M. Rafique, Zhichun Zhu
2018	A	`conf`	WALL: A writeback-aware LLC management for PCM-based main memory systems. DATE Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, Gokhan Memik
2017	—	`conf`	NEMO: an energy-efficient hybrid main memory system for mobile devices. MEMSYS Bahareh Pourshirazi, Zhichun Zhu
2016	A	`conf`	Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System. IPDPS Bahareh Pourshirazi, Zhichun Zhu
2014	—	`conf`	Access-Aware Memory Thermal Management. NAS Suyu Zhang, Zhichun Zhu
2014	J	`jnl`	Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture. IEEE Trans. Computers Kun Fang, Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu
2013	A	`conf`	Conservative row activation to improve memory power efficiency. ICS Kun Fang, Zhichun Zhu
2013	J	`jnl`	Thermal Modeling and Management of DRAM Systems. IEEE Trans. Computers Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang
2011	B	`conf`	Memory Architecture for Integrating Emerging Memory Technologies. PACT Kun Fang, Long Chen, Zhao Zhang, Zhichun Zhu
2010	B	`conf`	Heterogeneous Mini-rank: Adaptive, Power-Efficient Memory Architecture. ICPP Kun Fang, Hongzhong Zheng, Zhichun Zhu
2010	J	`jnl`	Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors. IEEE Trans. Computers Hongzhong Zheng, Zhichun Zhu
2009	A*	`conf`	Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. ISCA Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu
2008	B	`conf`	Memory Access Scheduling Schemes for Systems with Multi-Core Processors. ICPP Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu
2008	A*	`conf`	Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. MICRO Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, Zhichun Zhu
2008	A*	`conf`	Software thermal management of dram memory for multicore systems. SIGMETRICS Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Eugene Gorbatov, Howard David, Zhao Zhang
2007	B	`conf`	DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. ISPASS Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang, Howard David
2007	A*	`conf`	Thermal modeling and management of DRAM memory systems. ISCA Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang
2005	A*	`conf`	A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. HPCA Zhichun Zhu, Zhao Zhang
2005	J	`jnl`	Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption. IEEE Micro Zhichun Zhu, Xiaodong Zhang
2004	J	`jnl`	Design and Optimization of Large Size and Low Overhead Off-Chip Caches. IEEE Trans. Computers Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
2002	J	`jnl`	Access-Mode Predictions for Low-Power Cache Design. IEEE Micro Zhichun Zhu, Xiaodong Zhang
2002	A*	`conf`	Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. HPCA Zhichun Zhu, Zhao Zhang, Xiaodong Zhang
2001	J	`jnl`	Breaking Address Mapping Symmetry at Multi-levels of Memory Heirarchy to Reduce DRAM Row-buffer Conflicts. J. Instr. Level Parallelism Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
2001	J	`jnl`	Cached DRAM for ILP Processor Memory Access Latency Reduction. IEEE Micro Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
2000	A*	`conf`	A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. MICRO Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
2000	J	`jnl`	Memory Hierarchy Considerations for Cost-Effective Cluster Computing. IEEE Trans. Computers Xing Du, Xiaodong Zhang, Zhichun Zhu