Zhichuan Guo

17 papers Journal 17
YearRankTypeTitle / Venue / Authors
2026 J jnl
TRNIC: A High-Performance RDMA NIC with Triple-Table Bitmap for Efficient Out-of-Order Packet Reordering in Multipath Transmission.
IEICE Trans. Commun.
Mengting Zhang, Zhichuan Guo, Yipeng Pan, Jiandong Ma, Shining Sun
2025 J jnl
FPGA-Accelerated VXLAN Chaining for Partially Reconfigurable VNFs in Heterogeneous Data Centers.
IEICE Trans. Commun.
Yiwei Chang, Zhichuan Guo
2025 J jnl
Fuzzy-Based Deterministic Routing With Probabilistic Flooding in Underwater Acoustic Sensor Networks.
IEEE Internet Things J.
Bo Pang, Zhichuan Guo, Yating Liu
2025 J jnl
RoSR: A Novel Selective Retransmission FPGA Architecture for RDMA NICs.
IEEE Comput. Archit. Lett.
Mengting Zhang, Zhichuan Guo, Shining Sun
2025 J jnl
RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Yiwei Chang, Zhichuan Guo
2024 J jnl
An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaoyong Song, Zhichuan Guo
2024 J jnl
FPGA-based implementation of consistent flow configuration system for software-defined networking.
IEICE Electron. Express
Yiwei Chang, Zhichuan Guo, Yan Jiang
2024 J jnl
Fast Update Algorithm With Reorder Mechanism for SRAM-Based Longest Prefix Matching on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs
Xiaoyong Song, Zhichuan Guo
2024 J jnl
High-Throughput Exact Matching Implementation on FPGA with Shared Rule Tables Among Parallel Pipelines.
IEICE Trans. Commun.
Xiaoyong Song, Zhichuan Guo, Xinshuo Wang, Mangu Song
2023 J jnl
High Performance Network Virtualization Architecture on FPGA SmartNIC.
IEICE Trans. Commun.
Ke Wang, Yiwei Chang, Zhichuan Guo
2022 J jnl
FGLB: A fine-grained hardware intra-server load balancer based on 100 G FPGA SmartNIC.
Int. J. Netw. Manag.
Xiaoying Huang, Zhichuan Guo, Mangu Song
2021 J jnl
A Multifunctional Full-Packet Capture and Network Measurement System Supporting Nanosecond Timestamp and Real-Time Analysis.
IEEE Trans. Instrum. Meas.
Luchao Han, Zhichuan Guo, Xiaoying Huang, Xuewen Zeng
2021 J jnl
Accelerating the SM3 hash algorithm with CPU-FPGA Co-Designed architecture.
IET Comput. Digit. Tech.
Xiaoying Huang, Zhichuan Guo, Mangu Song, Xuewen Zeng
2020 J jnl
High-Performance Implementation of Dynamically Configurable Load Balancing Engine on FPGA.
IEEE Commun. Mag.
Jun Zhao, Zhichuan Guo, Xuewen Zeng, Mangu Song
2020 J jnl
Malware Traffic Classification Based on Recurrence Quantification Analysis.
Int. J. Netw. Secur.
Zheng-Zhi Tang, Xuewen Zeng, Zhichuan Guo, Mangu Song
2019 J jnl
High Throughput Implementation of SMS4 on FPGA.
IEEE Access
Jun Zhao, Zhichuan Guo, Xuewen Zeng
2012 J jnl
Efficient information hiding in H.264/AVC video coding.
Telecommun. Syst.
Ke Liao, Shiguo Lian, Zhichuan Guo, Jinlin Wang