Zhi Li

12 papers C 1Journal 7Unranked 4
YearRankTypeTitle / Venue / Authors
2026 — conf
30.6 A 16Mb 166.8TOPS/W Near-Memory Phase-Domain-Computing Ferroelectric NAND Flash for Approximate Nearest Neighbor Search on Edge Devices.
ISSCC
Weizeng Li, Bohan Wang, Zhidao Zhou, Junyu Zhu, Zhi Li, Junzhe Shen, Wenfeng Zha, Zhongze Han, Yiman Wang, Linfang Wang, Hongyang Hu, Qing Luo, Chunmeng Dou, Ming Liu
2026 — conf
A 12nm 4Mb 104.56-to-137.75TFLOPS/W Charge-Trap Transistor-Based Computing-in-Memory Macro Using Analog-Predict-Digital-Compute for AI Edge Devices.
ISSCC
Junzhe Shen, Zhidao Zhou, Wenfeng Zha, Zhi Li, Weizeng Li, Bohan Wang, Junyu Zhu, Hanghang Gao, Zhongze Han, Yiman Wang, Linfang Wang, Hongyang Hu, Qing Luo, Chunmeng Dou, Ming Liu
2026 J jnl
A hybrid-tiling attention accelerator with a fully-pipelined balanced systolic array in 3D hybrid-bonding near-DRAM integration.
Microelectron. J.
Zhongze Han, Hanghang Gao, Weizeng Li, Zhi Li, Zhidao Zhou, Yiman Wang, Junzhe Shen, Junyu Zhu, Bohan Wang, Jianguo Yang, Jinshan Yue, Hongyang Hu, Chunmeng Dou
2025 J jnl
A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Jun Wang, Shengzhe Yan, Xiangqu Fu, Zhihang Qian, Zhi Li, Zeyu Guo, Zhuoyu Dai, Zhaori Cong, Chunmeng Dou, Feng Zhang, Jinshan Yue, Dashan Shang
2025 J jnl
An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree.
IEEE Trans. Very Large Scale Integr. Syst.
Wang Ye, Hanghang Gao, Zhidao Zhou, Linfang Wang, Weizeng Li, Zhi Li, Jinshan Yue, Xiaoxin Xu, Jianguo Yang, Hongyang Hu, Chunmeng Dou
2025 J jnl
An energy-efficient FeFET-based computing-in-memory macro using BEOL-integrated HZO ferroelectric capacitors.
Sci. China Inf. Sci.
Weizeng Li, Zhidao Zhou, Linfang Wang, Junyu Zhu, Junzhe Shen, Hongyang Hu, Baihan Wang, Zhi Li, Wang Ye, Zhongze Han, Hanghang Gao, Chunmeng Dou
2025 J jnl
SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiangqu Fu, Jinshan Yue, Muhammad Faizan, Zhi Li, Qiang Huo, Feng Zhang
2024 — conf
34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process.
ISSCC
Linfang Wang, Weizeng Li, Zhidao Zhou, Hanghang Gao, Zhi Li, Wang Ye, Hongyang Hu, Jing Liu, Jinshan Yue, Jianguo Yang, Qing Luo, Chunmeng Dou, Qi Liu, Ming Liu
2024 C conf
A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators.
ISCAS
Weizeng Li, Linfang Wang, Zhi Li, Wang Ye, Zhidao Zhou, Haiyang Zhou, Hanghang Gao, Jinshan Yue, Hongyang Hu, Fengman Liu, Qing Luo, Chunmeng Dou
2024 — conf
First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s).
VLSI Technology and Circuits
Menggan Liu, Zhi Li, Wendong Lu, Kaifei Chen, Jiebin Niu, Fuxi Liao, Zijing Wu, Congyan Lu, Weizeng Li, Di Geng, Nianduan Lu, Chunmeng Dou, Guanhua Yang, Ling Li, Ming Liu
2024 J jnl
Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge.
IEEE Trans. Very Large Scale Integr. Syst.
Junjie An, Zhidao Zhou, Linfang Wang, Wang Ye, Weizeng Li, Hanghang Gao, Zhi Li, Jinghui Tian, Yan Wang, Hongyang Hu, Jinshan Yue, Lingyan Fan, Shibing Long, Qi Liu, Chunmeng Dou
2023 J jnl
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference.
IEEE J. Solid State Circuits
Wang Ye, Linfang Wang, Zhidao Zhou, Junjie An, Weizeng Li, Hanghang Gao, Zhi Li, Jinshan Yue, Hongyang Hu, Xiaoxin Xu, Jianguo Yang, Jing Liu, Dashan Shang, Feng Zhang, Jinghui Tian, Chunmeng Dou, Qi Liu, Ming Liu