Zhenyu Sun

15 papers A* 2A 5Journal 6Unranked 2
YearRankTypeTitle / Venue / Authors
2016 J jnl
Array Organization and Data Management Exploration in Racetrack Memory.
IEEE Trans. Computers
Zhenyu Sun, Xiuyuan Bi, Wenqing Wu, Sungjoo Yoo, Hai (Helen) Li
2016 J jnl
Spintronic Memristor as Interface Between DNA and Solid State Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Jianlei Yang, Zhenyu Sun, Xiaobin Wang, Yiran Chen, Hai Li
2015 J jnl
Read Performance: The Newest Barrier in Scaled STT-RAM.
IEEE Trans. Very Large Scale Integr. Syst.
Yaojun Zhang, Yong Li, Zhenyu Sun, Hai Li, Yiran Chen, Alex K. Jones
2015 — conf
The evolutionary spintronic technologies and their usage in high performance computing.
SoCC
Hai (Helen) Li, Xiuyuan Bi, Zhenyu Sun
2014 — conf
A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores.
ASP-DAC
Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong, Zhenyu Sun, Hai Li
2014 A conf
Design exploration of racetrack lower-level caches.
ISLPED
Zhenyu Sun, Xiuyuan Bi, Alex K. Jones, Hai Li
2014 J jnl
STT-RAM Cache Hierarchy With Multiretention MTJ Designs.
IEEE Trans. Very Large Scale Integr. Syst.
Zhenyu Sun, Xiuyuan Bi, Hai Li, Weng-Fai Wong, Xiaochun Zhu
2013 A* conf
Cross-layer racetrack memory design for ultra high density and low power consumption.
DAC
Zhenyu Sun, Wenqing Wu, Hai (Helen) Li
2012 A conf
A dual-mode architecture for fast-switching STT-RAM.
ISLPED
Zhenyu Sun, Hai Li, Wenqing Wu
2012 J jnl
Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder.
ACM J. Emerg. Technol. Comput. Syst.
Zhenyu Sun, Xiang Chen, Yaojun Zhang, Hai Li, Yiran Chen
2012 A conf
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.
ICCAD
Xiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu
2012 A conf
Process variation aware data management for STT-RAM cache design.
ISLPED
Zhenyu Sun, Xiuyuan Bi, Hai Li
2012 J jnl
Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang
2011 A* conf
Multi retention level STT-RAM cache designs with a dynamic refresh scheme.
MICRO
Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu
2010 A conf
Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement.
ICCAD
Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang