Zhengyu Chen

15 papers A* 2A 1C 1Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2025 — conf
Modeling, Design and In-situ Demonstration of Bio-inspired Central Pattern Generator and Neuromorphic Computing Circuits for Complex Kinematic Control of Quadruped Robots.
ACM Great Lakes Symposium on VLSI
Qiankai Cao, Yuhao Ju, Zhiwei Zhong, Zhengyu Chen, Jie Gu
2024 J jnl
Composition of Experts on the SN40L Reconfigurable Dataflow Unit.
IEEE Micro
Raghu Prabhakar, Ram Sivaramakrishnan, Darshan Gandhi, Yun Du, Mingran Wang, Xiangyu Song, Kejie Zhang, Tianren Gao, Angela Wang, Xiaoyan Li, Joshua Brot, Calvin Leung, Tuowen Zhao, Mark Gottscho, Zhengyu Chen, Kaizhao Liang, Swayambhoo Jain, Urmish Thakker, Kevin J. Brown, Kunle Olukotun
2024 A* conf
SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts.
MICRO
Raghu Prabhakar, Ram Sivaramakrishnan, Darshan Gandhi, Yun Du, Mingran Wang, Xiangyu Song, Kejie Zhang, Tianren Gao, Angela Wang, Xiaoyan Li, Yongning Sheng, Joshua Brot, Denis Sokolov, Apurv Vivek, Calvin Leung, Arjun Sabnis, Jiayu Bai, Tuowen Zhao, Mark Gottscho, David Jackson, Mark Luttrell, Manish K. Shah, Zhengyu Chen, Kaizhao Liang, Swayambhoo Jain, Urmish Thakker, Dawei Huang, Sumti Jairath, Kevin J. Brown, Kunle Olukotun
2023 — conf
AI SoC Design Challenges in the Foundation Model Era.
CICC
Zhengyu Chen, Dawei Huang, Mingran Wang, Bowen Yang, Jinuk Luke Shin, Changran Hu, Bo Li, Raghu Prabhakar, Gao Deng, Yongning Sheng, Sihua Fu, Lu Yuan, Tian Zhao, Yun Du, Chen Liu, Jun Yang, Viren Shah, Venkat Srinivasan, Sumti Jairath
2021 — conf
15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency.
ISSCC
Zhengyu Chen, Xi Chen, Jie Gu
2021 J jnl
High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing.
IEEE J. Solid State Circuits
Zhengyu Chen, Jie Gu
2020 — conf
A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices.
VLSI Circuits
Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu
2019 — conf
A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput.
ISSCC
Zhengyu Chen, Jie Gu
2019 J jnl
A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation.
IEEE J. Solid State Circuits
Zhengyu Chen, Jie Gu
2019 A* conf
Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing.
DAC
Zhengyu Chen, Hai Zhou, Jie Gu
2019 J jnl
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction.
IEEE Trans. Very Large Scale Integr. Syst.
Zhengyu Chen, Hai Zhou, Jie Gu
2018 J jnl
A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design.
IEEE Trans. Very Large Scale Integr. Syst.
Zhengyu Chen, Huanyu Wang, Geng Xie, Jie Gu
2018 — conf
An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation.
A-SSCC
Zhengyu Chen, Jie Gu
2018 C conf
R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing.
ICCD
Zhengyu Chen, Hai Zhou, Jie Gu
2016 A conf
Analysis and Design of Energy Efficient Time Domain Signal Processing.
ISLPED
Zhengyu Chen, Jie Gu