Zhengya Zhang - RankMe

130 papers A* 8A 8B 6C 6Misc 3Journal 53Unranked 46

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	2.5 A 1.1mm ISSCC Cheng-Hsun Lu, Wei Tang, Jaehee Kim, Youngjoo Lee, Zhengya Zhang
2026	—	`conf`	Medusa: A Quantum-Inspired 200-Variable 1016-Clause Analog k-SAT Solver. ISSCC Luke Wormald, Ying-Tuan Hsu, Evangelos Dikopoulos, Wei Tang, Benjamin Datsko, Ali Hammoud, Zhengya Zhang, Michael P. Flynn
2026	—	`conf`	UniC-Vision: A 14.4Gb/s 7.3pJ/b Universal Vision Transformer OFDM Channel Estimation Accelerator for B5G/6G AI-RAN. ISSCC Sangbu Yun, Chanhee Lee, Soonhyun Kwon, Jeongtaek Chang, Zhengya Zhang, Youngjoo Lee
2025	—	`conf`	25.1 A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100 ISSCC Evangelos Dikopoulos, Ying-Tuan Hsu, Luke Wormald, Wei Tang, Zhengya Zhang, Michael P. Flynn
2025	J	`jnl`	A cross-matrix arbiter PUF with high reliability and ML-resistance for IoT device security. Microelectron. J. Zhangqing He, Junming Zhang, Xinrui Zhu, Siyu Luo, Zhengya Zhang, Zhou Huang
2025	—	`conf`	Adaptive Attention-Based Model for 5G Radio-Based Outdoor Localization. IEEECONF Ilayda Yaman, Guoda Tian, Dino Pjanic, Fredrik Tufvesson, Ove Edfors, Zhengya Zhang, Liang Liu
2025	J	`jnl`	Adaptive Attention-Based Model for 5G Radio-based Outdoor Localization. CoRR Ilayda Yaman, Guoda Tian, Fredrik Tufvesson, Ove Edfors, Zhengya Zhang, Liang Liu
2025	J	`jnl`	An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing. IEEE J. Solid State Circuits Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Wei D. Lu, Zhengya Zhang, Michael P. Flynn
2025	J	`jnl`	Daedalus: A Physics-Inspired Mixed-Signal Optimization Engine With Dynamic Continuous-Time Injection for Solving 3-SAT Problems. IEEE J. Solid State Circuits Evangelos Dikopoulos, Ying-Tuan Hsu, Luke Wormald, Wei Tang, Benjamin Datsko, Zhengya Zhang, Michael P. Flynn
2025	J	`jnl`	Energy-Efficient Parallel Interconnects for Chiplet Integration. IEEE Micro Wei Tang, Chester Liu, Zhengya Zhang
2025	A*	`conf`	HiPER: Hierarchically-Composed Processing for Efficient Robot Learning-Based Control. ISCA Justin Ting, Minsik Kim, Junkang Zhu, Haotian Sheng, Zhengya Zhang
2025	A*	`conf`	Panacea: Novel DNN Accelerator using Accuracy-Preserving Asymmetric Quantization and Energy-Saving Bit-Slice Sparsity. HPCA Dongyun Kam, Myeongji Yun, Sunwoo Yoo, Seungwoo Hong, Zhengya Zhang, Youngjoo Lee
2025	A	`conf`	Practical MU-MIMO Detection and LDPC Decoding Through Digital Annealing. DATE Po-Shao Chen, Wei Tang, Zhengya Zhang
2025	J	`jnl`	RXO-LDPC: A Physics-Inspired Relaxation Oscillator-Based Solver Leveraging Six-Body Spin Interactions for Soft Decoding of LDPC Codes. IEEE J. Solid State Circuits Evangelos Dikopoulos, Luke Wormald, Ying-Tuan Hsu, Wei Tang, Po-Shao Chen, Zhengya Zhang, Michael P. Flynn
2025	J	`jnl`	SteROI-D: System Design and Mapping for Stereo Depth Inference on Regions of Interest. CoRR Jack Erhardt, Ziang Li, Reid Pinkham, Andrew Berkovich, Zhengya Zhang
2025	J	`jnl`	SteROI-D: System Design and Mapping for Stereo Depth Inference on Regions of Interest. IEEE Trans. Very Large Scale Integr. Syst. Jack Erhardt, Ziang Li, Reid Pinkham, Andrew Berkovich, Zhengya Zhang
2024	—	`conf`	2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications. ISSCC Dongyun Kam, Sangbu Yun, Jeongwon Choe, Zhengya Zhang, Namyoon Lee, Youngjoo Lee
2024	—	`conf`	An 11.4mm VLSI Technology and Circuits Cheng-Hsun Lu, Wei Tang, Jiyoon Han, Zhengya Zhang
2024	J	`jnl`	Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. IEEE J. Solid State Circuits Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang
2024	A	`conf`	Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems. ISLPED Vikram Jain, Wei Tang, Zuoguo Wu, Viansa Schmulbach, Yakun Sophia Shao, Zhengya Zhang, Borivoje Nikolic
2024	J	`jnl`	Panacea: Novel DNN Accelerator using Accuracy-Preserving Asymmetric Quantization and Energy-Saving Bit-Slice Sparsity. CoRR Dongyun Kam, Myeongji Yun, Sunwoo Yoo, Seungwoo Hong, Zhengya Zhang, Youngjoo Lee
2024	J	`jnl`	TT-CIM: Tensor Train Decomposition for Neural Network in RRAM-Based Compute-in-Memory Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Fan-Hsuan Meng, Yuting Wu, Zhengya Zhang, Wei D. Lu
2024	J	`jnl`	TetriX: Flexible Architecture and Optimal Mapping for Tensorized Neural Network Processing. IEEE Trans. Computers Jie-Fang Zhang, Cheng-Hsun Lu, Zhengya Zhang
2024	—	`conf`	Tiled Beamspace Processing for Scaling mmWave Massive MU-MIMO. VTC Fall Jiyoon Han, Canan Cebeci, Wei Tang, Zhengya Zhang, Upamanyu Madhow
2023	J	`jnl`	ANSA: Adaptive Near-Sensor Architecture for Dynamic DNN Processing in Compact Form Factors. IEEE Trans. Circuits Syst. I Regul. Pap. Reid Pinkham, Jack Erhardt, Barbara De Salvo, Andrew Berkovich, Zhengya Zhang
2023	A	`conf`	AR-PIM: An Adaptive-Range Processing-in-Memory Architecture. ISLPED Teyuh Chou, Fernando García-Redondo, Paul N. Whatmough, Zhengya Zhang
2023	—	`conf`	Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm VLSI Technology and Circuits Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang
2023	A*	`conf`	eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs. HPCA Junkang Zhu, Yaoyu Tao, Zhengya Zhang
2022	—	`conf`	An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. VLSI Technology and Circuits Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Zhengya Zhang, Wei D. Lu, Michael P. Flynn
2022	J	`jnl`	Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes. CoRR Yaoyu Tao, Shuanghong Sun, Zhengya Zhang
2022	J	`jnl`	HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer. CoRR Yaoyu Tao, Zhengya Zhang
2022	—	`conf`	NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging. VLSI Technology and Circuits Teyuh Chou, Wei Tang, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang
2022	J	`jnl`	TAICHI: A Tiled Architecture for In-Memory Computing and Heterogeneous Integration. IEEE Trans. Circuits Syst. II Express Briefs Xinxin Wang, Reid Pinkham, Mohammed Affan Zidan, Fan-Hsuan Meng, Michael P. Flynn, Zhengya Zhang, Wei D. Lu
2022	J	`jnl`	VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters. IEEE J. Solid State Circuits Junkang Zhu, Wei Tang, Ching-En Lee, Haolei Ye, Eric McCreath, Zhengya Zhang
2021	J	`jnl`	A 0.58-mm IEEE J. Solid State Circuits Wei Tang, Chia-Hsiang Chen, Zhengya Zhang
2021	—	`conf`	A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer. CICC Chester Liu, Jacob Botimer, Zhengya Zhang
2021	J	`jnl`	A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture. IEEE J. Solid State Circuits Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang
2021	B	`conf`	DNC-Aided SCL-Flip Decoding of Polar Codes. GLOBECOM Yaoyu Tao, Zhengya Zhang
2021	J	`jnl`	DNC-Aided SCL-Flip Decoding of Polar Codes. CoRR Yaoyu Tao, Zhengya Zhang
2021	—	`conf`	Exploration of Energy-Efficient Architecture for Graph-Based Point-Cloud Deep Learning. SiPS Jie-Fang Zhang, Zhengya Zhang
2021	A*	`conf`	HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer. MICRO Yaoyu Tao, Zhengya Zhang
2021	J	`jnl`	Near-Sensor Distributed DNN Processing for Augmented and Virtual Reality. IEEE J. Emerg. Sel. Topics Circuits Syst. Reid Pinkham, Andrew Berkovich, Zhengya Zhang
2021	—	`conf`	PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. VLSI Circuits Sung-Gun Cho, Wei Tang, Chester Liu, Zhengya Zhang
2021	A*	`conf`	Point-X: A Spatial-Locality-Aware Architecture for Energy-Efficient Graph-Based Point-Cloud Deep Learning. MICRO Jie-Fang Zhang, Zhengya Zhang
2021	J	`jnl`	SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. IEEE J. Solid State Circuits Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang
2021	—	`conf`	VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters. VLSI Circuits Junkang Zhu, Wei Tang, Ching-En Lee, Haolei Ye, Eric McCreath, Zhengya Zhang
2020	J	`jnl`	A 1.87-mm IEEE J. Solid State Circuits Thomas Chen, Jacob Botimer, Teyuh Chou, Zhengya Zhang
2020	A	`conf`	Control of Magnetically-Driven Screws in a Viscoelastic Medium. IROS Zhengya Zhang, Anke Klingner, Sarthak Misra, Islam S. M. Khalil
2020	A*	`conf`	QuickNN: Memory and Performance Optimization of k-d Tree Based Nearest Neighbor Search for 3D Point Clouds. HPCA Reid Pinkham, Shuqing Zeng, Zhengya Zhang
2019	J	`jnl`	A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification. IEEE J. Solid State Circuits Thomas Chen, Ching-En Lee, Chester Liu, Zhengya Zhang
2019	J	`jnl`	A 2.4-mm IEEE J. Solid State Circuits Wei Tang, Chia-Hsiang Chen, Zhengya Zhang
2019	—	`conf`	A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. CICC Sung-Gun Cho, Edith Beigné, Zhengya Zhang
2019	—	`conf`	A 3.25Gb/s, 13.2pJ/b, 0.64mm VLSI Circuits Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang
2019	—	`conf`	An Sram-Based Accelerator for Solving Partial Differential Equations. CICC Thomas Chen, Jacob Botimer, Teyuh Chou, Zhengya Zhang
2019	A*	`conf`	CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm. MICRO Teyuh Chou, Wei Tang, Jacob Botimer, Zhengya Zhang
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019	J	`jnl`	Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Yaoyu Tao, Shuanghong Sun, Zhengya Zhang
2019	—	`conf`	SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS. VLSI Circuits Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang
2018	—	`conf`	A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks. ESSCIRC Hsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou
2018	—	`conf`	A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI. ISSCC Wei Tang, Hemanth Prabhu, Liang Liu, Viktor Öwall, Zhengya Zhang
2018	J	`jnl`	A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles. IEEE J. Solid State Circuits Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin P. Kempke, Luyao Gong, Zhengya Zhang, Ronald G. Dreslinski, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim
2018	J	`jnl`	A 2.56-mm IEEE J. Solid State Circuits Chester Liu, Sung-Gun Cho, Zhengya Zhang
2018	J	`jnl`	A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link. IEEE Trans. Circuits Syst. I Regul. Pap. Shiming Song, Kyojin David Choo, Thomas Chen, Sunmin Jang, Michael P. Flynn, Zhengya Zhang
2018	J	`jnl`	Field-Programmable Crossbar Array (FPCA) for Reconfigurable Computing. IEEE Trans. Multi Scale Comput. Syst. Mohammed Affan Zidan, Yeonjoo Jeong, Jong Hoon Shin, Chao Du, Zhengya Zhang, Wei D. Lu
2018	—	`conf`	Inference and Learning Hardware Architecture for Neuro- Inspired Sparse Coding Algoerithm. BioCAS Chester Liu, Zhengya Zhang
2018	—	`conf`	LEIA: A 2.05mm CICC Shiming Song, Wei Tang, Thomas Chen, Zhengya Zhang
2018	—	`conf`	Optimizing a Fuzzy Equivalent Sliding Mode Control Applied to Servo Drive Systems. SOCO-CISIS-ICEUTE Zhengya Zhang, Matilde Santos
2017	—	`conf`	20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS. ISSCC Hsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou
2017	—	`conf`	3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation. ISSCC Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin P. Kempke, Shijia Yang, Zhengya Zhang, Ronald G. Dreslinski, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim
2017	—	`conf`	A 1.25pJ/bit 0.048mm A-SSCC Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
2017	J	`jnl`	A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging. IEEE J. Solid State Circuits John Bell, Phil Knag, Shuanghong Sun, Yong Lim, Thomas Chen, Jeffrey Fredenburg, Chia-Hsiang Chen, Chunyang Zhai, Aaron Z. Rocca, Nicholas Collins, Andres Tamez, Jorge Pernillo, Justin M. Correll, Alan B. Tanner, Zhengya Zhang, Michael P. Flynn
2017	—	`conf`	A 2.56mm A-SSCC Chester Liu, Sung-Gun Cho, Zhengya Zhang
2017	J	`jnl`	Designing Practical Polar Codes Using Simulation-Based Bit Selection. IEEE J. Emerg. Sel. Topics Circuits Syst. Shuanghong Sun, Zhengya Zhang
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	B	`conf`	Post-Processing Methods for Improving Coding Gain in Belief Propagation Decoding of Polar Codes. GLOBECOM Shuanghong Sun, Sung-Gun Cho, Zhengya Zhang
2016	J	`jnl`	3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication. J. Signal Process. Syst. Farhana Sheikh, Chia-Hsiang Chen, Dongmin Yoon, Borislav Alexandrov, Keith A. Bowman, Anthony Chun, Hossein Alavi, Zhengya Zhang
2016	—	`conf`	A 0.58mm VLSI Circuits Wei Tang, Chia-Hsiang Chen, Zhengya Zhang
2016	—	`conf`	A 1.40mm VLSI Circuits Phil Knag, Chester Liu, Zhengya Zhang
2016	C	`conf`	A 180 GHz prototype for a geostationary microwave imager/sounder-GeoSTAR-III. IGARSS Todd Gaier, Pekka Kangaslahti, Bjorn Lambrigtsen, Isaac Ramos-Pérez, Alan B. Tanner, Darren McKague, Christopher Ruf, Michael J. Flynn, Zhengya Zhang, Roger Backhus, David Austerberry
2016	—	`conf`	A 5.5GHz 0.84TOPS/mm A-SSCC Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
2016	A*	`conf`	A Simple Generic Attack on Text Captchas. NDSS Haichang Gao, Jeff Yan, Fang Cao, Zhengya Zhang, Lei Lei, Mengyun Tang, Ping Zhang, Xin Zhou, Xuqin Wang, Jiawei Li
2016	C	`conf`	Architecture and optimization of high-throughput belief propagation decoding of polar codes. ISCAS Shuanghong Sun, Zhengya Zhang
2016	Misc	`conf`	Error patterns in belief propagation decoding of polar codes and their mitigation methods. ACSSC Shuanghong Sun, Sung-Gun Cho, Zhengya Zhang
2016	J	`jnl`	Field-Programmable Crossbar Array (FPCA) for Reconfigurable Computing. CoRR Mohammed Affan Zidan, Yeonjoo Jeong, Jong Hoon Shin, Chao Du, Zhengya Zhang, Wei D. Lu
2016	J	`jnl`	Robustness of text-based completely automated public turing test to tell computers and humans apart. IET Inf. Secur. Haichang Gao, Xuqin Wang, Fang Cao, Zhengya Zhang, Lei Lei, Jiao Qi, Xiyang Liu
2015	—	`conf`	1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks. VLSIC Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
2015	—	`conf`	18.7 A 2.4mm ISSCC Chia-Hsiang Chen, Wei Tang, Zhengya Zhang
2015	—	`conf`	A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning. VLSIC Jung Kuk Kim, Phil Knag, Thomas Chen, Zhengya Zhang
2015	—	`conf`	A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors. A-SSCC Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou
2015	J	`jnl`	A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating. IEEE J. Solid State Circuits Youn Sung Park, Yaoyu Tao, Zhengya Zhang
2015	J	`jnl`	A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding. IEEE J. Solid State Circuits Phil Knag, Jung Kuk Kim, Thomas Chen, Zhengya Zhang
2015	J	`jnl`	An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation. IEEE Trans. Circuits Syst. II Express Briefs Chia-Hsiang Chen, Shiming Song, Zhengya Zhang
2015	J	`jnl`	An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring. IEEE J. Solid State Circuits Yen-Po Chen, Dongsuk Jeon, Yoonmyung Lee, Yejoong Kim, Zhiyoong Foo, Inhee Lee, Nicholas B. Langhals, Grant H. Kruger, Hakan Oral, Omer Berenfeld, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
2014	—	`conf`	24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis. ISSCC Dongsuk Jeon, Yen-Po Chen, Yoonmyung Lee, Yejoong Kim, Zhiyoong Foo, Grant H. Kruger, Hakan Oral, Omer Berenfeld, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
2014	—	`conf`	27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder. ISSCC Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou
2014	—	`conf`	3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication. SiPS Farhana Sheikh, Chia-Hsiang Chen, Dongmin Yoon, Borislav Alexandrov, Keith A. Bowman, Anthony Chun, Hossein Alavi, Zhengya Zhang
2014	—	`conf`	A 4.68Gb/s belief propagation polar decoder with bit-splitting register file. VLSIC Youn Sung Park, Yaoyu Tao, Shuanghong Sun, Zhengya Zhang
2014	—	`conf`	A 6.67mW sparse coding ASIC enabling on-chip learning and inference. VLSIC Jung Kuk Kim, Phil Knag, Thomas Chen, Zhengya Zhang
2014	J	`jnl`	An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS. IEEE J. Solid State Circuits Dongsuk Jeon, Michael B. Henry, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
2014	J	`jnl`	Design and Evaluation of Confidence-Driven Error-Resilient Systems. IEEE Trans. Very Large Scale Integr. Syst. Chia-Hsiang Chen, David T. Blaauw, Dennis Sylvester, Zhengya Zhang
2014	J	`jnl`	Efficient Hardware Architecture for Sparse Coding. IEEE Trans. Signal Process. Jung Kuk Kim, Phil Knag, Thomas Chen, Zhengya Zhang
2014	J	`jnl`	Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM. IEEE J. Solid State Circuits Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang
2014	C	`conf`	Memristive devices for stochastic computing. ISCAS Siddharth Gaba, Phil Knag, Zhengya Zhang, Wei Lu
2013	—	`conf`	A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. ISSCC Youn Sung Park, Yaoyu Tao, Zhengya Zhang
2013	—	`conf`	A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS. ISSCC Dongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
2013	Misc	`conf`	A low-power VGA full-frame feature extraction processor. ICASSP Dongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
2013	A	`conf`	An FPGA-based transient error simulator for evaluating resilient system designs (abstract only). FPGA Chia-Hsiang Chen, Shiming Song, Zhengya Zhang
2013	C	`conf`	Efficient in situ error detection enabling diverse path coverage. ISCAS Chia-Hsiang Chen, Yaoyu Tao, Zhengya Zhang
2013	A	`conf`	Minimum supply voltage for sequential logic circuits in a 22nm technology. ISLPED Chia-Hsiang Chen, Keith A. Bowman, Charles Augustine, Zhengya Zhang, Jim Tschanz
2012	—	`conf`	A 1.6-mm VLSIC Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang
2012	J	`jnl`	Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems. IEEE Trans. Circuits Syst. II Express Briefs Dongsuk Jeon, Mingoo Seok, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
2012	J	`jnl`	Forward-Projection Architecture for Fast Iterative Image Reconstruction in X-Ray CT. IEEE Trans. Signal Process. Jung Kuk Kim, Jeffrey A. Fessler, Zhengya Zhang
2012	C	`conf`	High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders. ISCAS Yaoyu Tao, Youn Sung Park, Zhengya Zhang
2012	A	`conf`	Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation. FPGA Haoran Li, Youn Sung Park, Zhengya Zhang
2012	J	`jnl`	The Cycle Consistency Matrix Approach to LDPC Absorbing Sets in Separable Circulant-Based Codes CoRR Jiadong Wang, Lara Dolecek, Zhengya Zhang, Richard D. Wesel
2011	A	`conf`	A confidence-driven model for error-resilient computing. DATE Chia-Hsiang Chen, Yejoong Kim, Zhengya Zhang, David T. Blaauw, Dennis Sylvester, Helia Naeimi, Sumeet Sandhu
2011	J	`jnl`	Absorbing Set Spectrum Approach for Practical Code Design CoRR Jiadong Wang, Lara Dolecek, Zhengya Zhang, Richard D. Wesel
2011	B	`conf`	Absorbing set spectrum approach for practical code design. ISIT Jiadong Wang, Lara Dolecek, Zhengya Zhang, Richard D. Wesel
2011	Misc	`conf`	Hardware acceleration of iterative image reconstruction for X-ray computed tomography. ICASSP Jung Kuk Kim, Zhengya Zhang, Jeffrey A. Fessler
2011	C	`conf`	LDPC decoder architecture for high-data rate personal-area networks. ISCAS Matthew Weiner, Borivoje Nikolic, Zhengya Zhang
2010	J	`jnl`	An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors. IEEE J. Solid State Circuits Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolic
2010	J	`jnl`	Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes. IEEE Trans. Inf. Theory Lara Dolecek, Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolic
2009	J	`jnl`	Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices. IEEE Trans. Commun. Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Venkat Anantharam, Martin J. Wainwright
2009	J	`jnl`	Predicting error floors of structured LDPC codes: deterministic bounds and estimates. IEEE J. Sel. Areas Commun. Lara Dolecek, Pamela Lee, Zhengya Zhang, Venkat Anantharam, Borivoje Nikolic, Martin J. Wainwright
2008	B	`conf`	Error floors in LDPC codes: Fast simulation, bounds and hardware emulation. ISIT Pamela Lee, Lara Dolecek, Zhengya Zhang, Venkat Anantharam, Borivoje Nikolic, Martin J. Wainwright
2008	B	`conf`	Lowering LDPC Error Floors by Postprocessing. GLOBECOM Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Venkat Anantharam, Martin J. Wainwright
2007	—	`conf`	Analysis of Absorbing Sets for Array-Based LDPC Codes. ICC Lara Dolecek, Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolic
2007	—	`conf`	Peak-to-Average Power Ratio Reduction in an FDM Broadcast System. SiPS Zhengya Zhang, Renaldi Winoto, Ahmad Bahai, Borivoje Nikolic
2007	—	`conf`	Quantization Effects in Low-Density Parity-Check Decoders. ICC Zhengya Zhang, Lara Dolecek, Martin J. Wainwright, Venkat Anantharam, Borivoje Nikolic
2006	B	`conf`	Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation. GLOBECOM Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Venkat Anantharam, Martin J. Wainwright