Zhen-guo Ma

13 papers Journal 13
YearRankTypeTitle / Venue / Authors
2020 J jnl
FPGA-Accelerated Hash Join Operation for Relational Databases.
IEEE Trans. Circuits Syst. II Express Briefs
Meiting Xue, Qianjian Xing, Chen Feng, Feng Yu, Zhen-guo Ma
2020 J jnl
High-Throughput Parallel SRAM-Based Hash Join Architecture on FPGA.
IEEE Trans. Circuits Syst.
Wen-Qi Wu, Meiting Xue, Tian-Qi Zhu, Zhen-guo Ma, Feng Yu
2019 J jnl
Pipelined Algorithm and Modular Architecture for Matrix Transposition.
IEEE Trans. Circuits Syst. II Express Briefs
Yunxiang Wang, Zhen-guo Ma, Feng Yu
2019 J jnl
Resource-Efficient Parallel Tree-Based Join Architecture on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs
Huan Zhang, Bei Zhao, Wei-Jun Li, Zhen-guo Ma, Feng Yu
2018 J jnl
A Fused Continuous Floating-Point MAC on FPGA.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Min Yuan, Qianjian Xing, Zhen-guo Ma, Feng Yu, Yingke Xu
2017 J jnl
A Continuous-Flow Memory-Based Architecture for Real-Valued FFT.
IEEE Trans. Circuits Syst. II Express Briefs
Xiubin Mao, Zhen-guo Ma, Feng Yu, Qianjian Xing
2017 J jnl
A Novel Conflict-Free Parallel Memory Access Scheme for FFT Processors.
IEEE Trans. Circuits Syst. II Express Briefs
Qianjian Xing, Zhen-guo Ma, Yingke Xu
2017 J jnl
A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Qianjian Xing, Zhen-guo Ma, Feng Yu
2016 J jnl
Efficient Circuit for Parallel Bit Reversal.
IEEE Trans. Circuits Syst. II Express Briefs
Weijun Li, Feng Yu, Zhen-guo Ma
2016 J jnl
Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths.
IEEE Trans. Circuits Syst. II Express Briefs
Xiaobo Yin, Feng Yu, Zhen-guo Ma
2016 J jnl
Time Delay Estimation via Co-Prime Aliased Sparse FFT.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Bei Zhao, Chen Cheng, Zhen-guo Ma, Feng Yu
2015 J jnl
A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs
Zhen-guo Ma, Xiaobo Yin, Feng Yu
2011 J jnl
An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays.
J. Zhejiang Univ. Sci. C
Zhen-guo Ma, Feng Yu, Ruifeng Ge, Zeke Wang