Zhehong Wang - RankMe

20 papers A* 1Journal 9Unranked 10

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	LECLIP: Boosting Zero-Shot Anomaly Detection With Local Enhanced CLIP. IEEE Trans. Instrum. Meas. Yuyao Liu, Qingyong Li, Zhehong Wang, Jien Kato, Jie Zhang, Wen Wang
2025	J	`jnl`	PDMA: Efficient and privacy-preserving dynamic task assignment with multi-attribute search in crowdsourcing. Comput. Networks Haiyong Bao, Ronghai Xie, Zhehong Wang, Lu Xing, Hong-Ning Dai
2025	J	`jnl`	TAMT: Privacy-Preserving Task Assignment With Multi-Threshold Range Search for Spatial Crowdsourcing Applications. IEEE Trans. Big Data Haiyong Bao, Zhehong Wang, Rongxing Lu, Cheng Huang, Beibei Li
2024	—	`conf`	A Heterogeneous Federated Learning Method Based on Dual Teachers Knowledge Distillation. ADMA (2) Siyuan Wu, Hao Tian, Weiran Zhang, Tingtong Zhu, Fuwen Tian, Zhehong Wang, Wanchun Dou
2024	J	`jnl`	AIMMI: Audio and Image Multi-Modal Intelligence via a Low-Power SoC With 2-MByte On-Chip MRAM for IoT Devices. IEEE J. Solid State Circuits Zichen Fan, Qirui Zhang, Hyochan An, Boxun Xu, Li Xu, Chien-Wei Tseng, Yimai Peng, Andrea Bejarano-Carbo, Pierre Abillama, Ang Cao, Bowen Liu, Changwoo Lee, Zhehong Wang, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester
2024	J	`jnl`	RoboVisio: A Micro-Robot Vision Domain-Specific SoC for Autonomous Navigation Enabling Fully-on-Chip Intelligence via 2-MB eMRAM. IEEE J. Solid State Circuits Qirui Zhang, Zichen Fan, Hyochan An, Zhehong Wang, Ziyun Li, Guanru Wang, Pierre Abillama, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester
2022	—	`conf`	A 22nm 3.5TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip Intelligence. VLSI Technology and Circuits Qirui Zhang, Hyochan An, Zichen Fan, Zhehong Wang, Ziyun Li, Guanru Wang, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester
2022	—	`conf`	Audio and Image Cross-Modal Intelligence via a 10TOPS/W 22nm SoC with Back-Propagation and Dynamic Power Gating. VLSI Technology and Circuits Zichen Fan, Hyochan An, Qirui Zhang, Boxun Xu, Li Xu, Chien-Wei Tseng, Yimai Peng, Ang Cao, Bowen Liu, Changwoo Lee, Zhehong Wang, FangHao Liu, Guanru Wang, Shenghao Jiang, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester
2022	J	`jnl`	Hardware Acceleration for Third-Generation FHE and PSI Based on It. CoRR Zhehong Wang, Dennis Sylvester, Hun-Seok Kim, David T. Blaauw
2021	J	`jnl`	A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array. IEEE J. Solid State Circuits Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw
2021	J	`jnl`	RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator. IEEE J. Solid State Circuits Ziyun Li, Zhehong Wang, Li Xu, Qing Dong, Bowen Liu, Chin-I Su, Wen-Ting Chu, George Tsou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Dennis Sylvester, Hun-Seok Kim, David T. Blaauw
2020	—	`conf`	17.3 GCUPS Pruning-Based Pair-Hidden-Markov-Model Accelerator for Next-Generation DNA Sequencing. VLSI Circuits Xiao Wu, Arun Subramaniyan, Zhehong Wang, Satish Narayanasamy, Reetu Das, David T. Blaauw
2020	—	`conf`	A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array. CICC Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw
2020	—	`conf`	AA-ResNet: Energy Efficient All-Analog ResNet Accelerator. MWSCAS Jongyup Lim, Myungjoon Choi, Bowen Liu, Taewook Kang, Ziyun Li, Zhehong Wang, Yiqun Zhang, Kaiyuan Yang, David T. Blaauw, Hun-Seok Kim, Dennis Sylvester
2020	—	`conf`	An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM. VLSI Circuits Zhehong Wang, Ziyun Li, Li Xu, Qing Dong, Chin-I Su, Wen-Ting Chu, George Tsou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Dennis Sylvester, Hun-Seok Kim, David T. Blaauw
2019	J	`jnl`	A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination. IEEE J. Solid State Circuits Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Mahmut E. Sinangil, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester
2019	A*	`conf`	Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. DAC Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu
2018	—	`conf`	A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination. ISSCC Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester
2018	—	`conf`	A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM. VLSI Circuits Kaiyuan Yang, Qing Dong, Zhehong Wang, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester
2018	—	`conf`	Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT Applications. VLSI Circuits Supreet Jeloka, Zhehong Wang, Ruochen Xie, Sudhanshu Khanna, Steven Bartling, Dennis Sylvester, David T. Blaauw