Zhe Wang

21 papers A* 10B 2C 1Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2025 A* conf
Push Multicast: A Speculative and Coherent Interconnect for Mitigating Manycore CPU Communication Bottleneck.
HPCA
Jiayi Huang, Yanhua Chen, Zhe Wang, Christopher J. Hughes, Yufei Ding, Yuan Xie
2025 A* conf
Software Prefetch Multicast: Sharer-Exposed Prefetching for Bandwidth Efficiency in Manycore Processors.
MICRO
Yanhua Chen, Jiong Feng, Zhe Wang, Christopher J. Hughes, Jiayi Huang
2024 J jnl
Agile C-states: A Core C-state Architecture for Latency Critical Applications Optimizing both Transition and Cold-Start Latency.
ACM Trans. Archit. Code Optim.
Georgia Antoniou, Davide B. Bartolini, Haris Volos, Marios Kleanthous, Zhe Wang, Kleovoulos Kalaitzidis, Tom Rollet, Ziwei Li, Onur Mutlu, Yiannakis Sazeides, Jawad Haj-Yahya
2022 A* conf
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications.
MICRO
Jawad Haj-Yahya, Haris Volos, Davide B. Bartolini, Georgia Antoniou, Jeremie S. Kim, Zhe Wang, Kleovoulos Kalaitzidis, Tom Rollet, Zhirui Chen, Ye Geng, Onur Mutlu, Yiannakis Sazeides
2022 J jnl
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications.
CoRR
Jawad Haj-Yahya, Haris Volos, Davide B. Bartolini, Georgia Antoniou, Jeremie S. Kim, Zhe Wang, Kleovoulos Kalaitzidis, Tom Rollet, Zhirui Chen, Ye Geng, Onur Mutlu, Yiannakis Sazeides
2022 J jnl
Going Further With Winograd Convolutions: Tap-Wise Quantization for Efficient Inference on 4x4 Tile.
CoRR
Renzo Andri, Beatrice Bussolino, Antonio Cipolletta, Lukas Cavigelli, Zhe Wang
2022 A* conf
Going Further With Winograd Convolutions: Tap-Wise Quantization for Efficient Inference on 4x4 Tiles.
MICRO
Renzo Andri, Beatrice Bussolino, Antonio Cipolletta, Lukas Cavigelli, Zhe Wang
2022 J jnl
Identifying and Exploiting Sparse Branch Correlations for Optimizing Branch Prediction.
CoRR
Anastasios Zouzias, Kleovoulos Kalaitzidis, Konstantin Berestizshevsky, Renzo Andri, Leeor Peled, Zhe Wang
2018 — conf
Flexible associativity for DRAM caches.
CF
Elvira Teran, Zeshan Chishti, Zhe Wang, Chris Wilkerson, Daniel A. Jiménez
2017 A* conf
Detecting and mitigating data-dependent DRAM failures by exploiting current memory content.
MICRO
Samira Manabi Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, Onur Mutlu
2016 C conf
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.
SBAC-PAD
Zhe Wang, Daniel A. Jiménez, Tao Zhang, Gabriel H. Loh, Yuan Xie
2016 A* conf
Minimal disturbance placement and promotion.
HPCA
Elvira Teran, Yingying Tian, Zhe Wang, Daniel A. Jiménez
2016 A* conf
Perceptron learning for reuse prediction.
MICRO
Elvira Teran, Zhe Wang, Daniel A. Jiménez
2014 A* conf
Adaptive placement and migration policy for an STT-RAM-based hybrid cache.
HPCA
Zhe Wang, Daniel A. Jiménez, Cong Xu, Guangyu Sun, Yuan Xie
2013 J jnl
WADE: Writeback-aware dynamic cache management for NVM-based main memory system.
ACM Trans. Archit. Code Optim.
Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie, Daniel A. Jiménez
2012 A* conf
Decoupled dynamic cache segmentation.
HPCA
Samira Manabi Khan, Zhe Wang, Daniel A. Jiménez
2012 A* conf
Improving writeback efficiency with decoupled last-write prediction.
ISCA
Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez
2012 — conf
Rank idle time prediction driven last-level cache writeback.
MSPC
Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez
2011 B conf
Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback.
PACT
Zhe Wang, Daniel A. Jiménez
2011 B conf
Program Interferometry.
PACT
Zhe Wang, Daniel A. Jiménez
2011 — conf
Program Interferometry.
IISWC
Zhe Wang, Daniel A. Jiménez