Zhe Lin

26 papers A* 1A 5B 1C 1Misc 1Journal 16Unranked 1
YearRankTypeTitle / Venue / Authors
2025 A conf
HIPPO: A Hierarchy-Preserving and Noise-Tolerant Pre-HLS Power Modeling Framework for FPGA.
ICCAD
Zefan Lin, Zedong Peng, Mingzhe Gao, Jieru Zhao, Zhe Lin
2025 A conf
TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms.
FPGA
Enlai Li, Zhe Lin, Sharad Sinha, Wei Zhang
2024 C conf
AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs.
ICCD
Mingzhe Gao, Jieru Zhao, Zhe Lin, Wenchao Ding, Xiaofeng Hou, Yu Feng, Chao Li, Minyi Guo
2024 J jnl
AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs.
CoRR
Mingzhe Gao, Jieru Zhao, Zhe Lin, Wenchao Ding, Xiaofeng Hou, Yu Feng, Chao Li, Minyi Guo
2024 J jnl
Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jian Peng, Tingyuan Liang, Jingbo Jiang, Yipu Zhang, Zhe Lin, Zhiyao Xie, Wei Zhang
2024 A conf
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network.
FPGA
Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang
2024 A conf
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs.
DATE
Mingzhe Gao, Jieru Zhao, Zhe Lin, Minyi Guo
2024 J jnl
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs.
CoRR
Mingzhe Gao, Jieru Zhao, Zhe Lin, Minyi Guo
2023 J jnl
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang
2023 A* conf
MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems.
DAC
Guan Shen, Jieru Zhao, Zeke Wang, Zhe Lin, Wenchao Ding, Chentao Wu, Quan Chen, Minyi Guo
2023 J jnl
MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems.
CoRR
Guan Shen, Jieru Zhao, Zeke Wang, Zhe Lin, Wenchao Ding, Chentao Wu, Quan Chen, Minyi Guo
2022 A conf
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs.
DATE
Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, Yonghong Tian
2022 J jnl
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs.
CoRR
Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, Yonghong Tian
2021 J jnl
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhe Lin, Sharad Sinha, Wei Zhang
2021 J jnl
PanGu-α: Large-scale Autoregressive Pretrained Chinese Language Models with Auto-parallel Computation.
CoRR
Wei Zeng, Xiaozhe Ren, Teng Su, Hui Wang, Yi Liao, Zhiwei Wang, Xin Jiang, ZhenZhang Yang, Kaisheng Wang, Xiaoda Zhang, Chen Li, Ziyan Gong, Yifan Yao, Xinjing Huang, Jun Wang, Jianfeng Yu, Qi Guo, Yue Yu, Yan Zhang, Jin Wang, Hengtao Tao, Dasen Yan, Zexuan Yi, Fang Peng, Fangqing Jiang, Han Zhang, Lingfeng Deng, Yehong Zhang, Zhe Lin, Chao Zhang, Shaojie Zhang, Mingyue Guo, Shanzhi Gu, Gaojun Fan, Yaowei Wang, Xuefeng Jin, Qun Liu, Yonghong Tian
2020 J jnl
An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power.
CoRR
Zhe Lin, Sharad Sinha, Wei Zhang
2020 J jnl
Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA.
CoRR
Zhe Lin, Wei Zhang, Sharad Sinha
2020 — conf
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis.
ASP-DAC
Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang
2020 J jnl
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis.
CoRR
Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang
2020 J jnl
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System.
CoRR
Zhe Lin, Sharad Sinha, Wei Zhang
2020 J jnl
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.
CoRR
Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang
2020 J jnl
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA.
CoRR
Zhe Lin, Sharad Sinha, Wei Zhang
2019 J jnl
An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhe Lin, Sharad Sinha, Wei Zhang
2019 Misc conf
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA.
FCCM
Zhe Lin, Sharad Sinha, Wei Zhang
2018 J jnl
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.
IEEE Trans. Multi Scale Comput. Syst.
Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang
2017 B conf
Decision tree based hardware power monitoring for run time dynamic power management in FPGA.
FPL
Zhe Lin, Wei Zhang, Sharad Sinha