Zhe Jiang

99 papers A* 22A 12B 3C 1Misc 2Journal 54Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
AkiraRust: Re-thinking LLM-aided Rust Repair Using a Feedback-guided Thinking Switch.
CoRR
Renshuang Jiang, Yichong Wang, Pan Dong, XiaoXiang Fang, Zhenling Duan, Tinglue Wang, Yuchen Hu, Jie Yu, Zhe Jiang
2026 J jnl
CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-exploration.
CoRR
Jinwu Chen, Yuhui Shi, He Wang, Zhe Jiang, Jun Yang, Xin Si, Zhenhua Zhu
2026 A* conf
ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications.
AAAI
Changwen Xing, SamZaak Wong, Xinlai Wan, Yanfeng Lu, Mengli Zhang, Zebin Ma, Lei Qi, Zhengxiong Li, Nan Guan, Zhe Jiang, Xi Wang, Jun Yang
2026 A* conf
FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification.
AAAI
Gwok-Waa Wan, SamZaak Wong, Shengchu Su, Chenxu Niu, Ning Wang, Xinlai Wan, Qixiang Chen, Mengnv Xing, Jingyi Zhang, Jianmin Ye, Yubo Wang, Rongchang Song, Tao Ni, Qiang Xu, Nan Guan, Zhe Jiang, Xi Wang, Yong Chen, Jun Yang
2026 J jnl
Joint learning video segmentation with different prior guidance.
J. Syst. Archit.
Dawei Yang, Chenhao Ma, Xiuhui Deng, Jason Junwei Zeng, Jianning Zhang, Wei Huang, Zhe Jiang, Ying Huo
2026 J jnl
NLI:Non-uniform Linear Interpolation Approximation of Nonlinear Operations for Efficient LLMs Inference.
CoRR
Jiangyong Yu, Xiaomeng Han, Xing Hu, Chen Xu, Zhe Jiang, Dawei Yang
2025 J jnl
ARSP: Automated Repair of Verilog Designs via Semantic Partitioning.
CoRR
Bingkun Yao, Ning Wang, Xiangfeng Liu, Yuxin Du, Yuchen Hu, Hong Gao, Zhe Jiang, Nan Guan
2025 A* conf
Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs.
DAC
Bingkun Yao, Mun Choon Chan, Hong Gao, Zhe Jiang, Nan Guan
2025 A* conf
BBAL: A Bidirectional Block Floating Point-Based Quantisation Accelerator for Large Language Models.
DAC
Xiaomeng Han, Yuan Cheng, Jing Wang, Junyang Lu, Hui Wang, X. x. Zhang, Ning Xu, Dawei Yang, Zhe Jiang
2025 J jnl
ChatModel: Automating Reference Model Design and Verification with LLMs.
CoRR
Jianmin Ye, Tianyang Liu, Qi Tian, Shengchu Su, Zhe Jiang, Xi Wang
2025 J jnl
ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications.
CoRR
Changwen Xing, SamZaak Wong, Xinlai Wan, Yanfeng Lu, Mengli Zhang, Zebin Ma, Lei Qi, Zhengxiong Li, Nan Guan, Zhe Jiang, Xi Wang, Jun Yang
2025 J jnl
Exploiting the Uncertainty of the Longest Paths: Response Time Analysis for Probabilistic DAG Tasks.
CoRR
Yiyang Gao, Shuai Zhao, Boyang Li, Xinwei Fang, Zhiyang Lin, Zhe Jiang, Nan Guan
2025 J jnl
FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification.
CoRR
Gwok-Waa Wan, Shengchu Su, Ruihu Wang, Qixiang Chen, Sam-Zaak Wong, Mengnv Xing, Hefei Feng, Yubo Wang, Yinan Zhu, Jingyi Zhang, Jianmin Ye, Xinlai Wan, Tao Ni, Qiang Xu, Nan Guan, Zhe Jiang, Xi Wang, Yang Jun
2025 A* conf
FireGuard: A Generalized Microarchitecture for Fine-Grained Security Analysis on OoO Superscalar Cores.
DAC
Zhe Jiang, Sam Ainsworth, Timothy M. Jones
2025 J jnl
FireGuard: A Generalized Microarchitecture for Fine-Grained Security Analysis on OoO Superscalar Cores.
CoRR
Zhe Jiang, Sam Ainsworth, Timothy M. Jones
2025 A* conf
FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems.
DAC
Tinglue Wang, Yiming Li, Wei Tang, Jiapeng Guan, Zhenghui Guo, Renshuang Jiang, Ran Wei, Jing Li, Zhe Jiang
2025 A conf
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification.
ICCAD
Junhao Ye, Yuchen Hu, Ke Xu, Dingrong Pan, Qichun Chen, Jie Zhou, Shuai Zhao, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang
2025 J jnl
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification.
CoRR
Junhao Ye, Yuchen Hu, Ke Xu, Dingrong Pan, Qichun Chen, Jie Zhou, Shuai Zhao, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang
2025 A* conf
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design.
DAC
Jie Zhou, Youshu Ji, Ning Wang, Yuchen Hu, Xinyao Jiao, Bingkun Yao, Xinwei Fang, Shuai Zhao, Nan Guan, Zhe Jiang
2025 A* conf
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design.
DAC
Jie Zhou, Youshu Ji, Ning Wang, Yuchen Hu, Xinyao Jiao, Bingkun Yao, Xinwei Fang, Shuai Zhao, Nan Guan, Zhe Jiang
2025 J jnl
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design.
CoRR
Jie Zhou, Youshu Ji, Ning Wang, Yuchen Hu, Xinyao Jiao, Bingkun Yao, Xinwei Fang, Shuai Zhao, Nan Guan, Zhe Jiang
2025 J jnl
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback.
CoRR
Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, Zhe Jiang
2025 A* conf
Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design.
DAC
Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan
2025 A* conf
MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors.
DAC
Zhe Jiang, Minli Liao, Sam Ainsworth, Dean You, Timothy M. Jones
2025 J jnl
MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors.
CoRR
Zhe Jiang, Minli Liao, Sam Ainsworth, Dean You, Timothy M. Jones
2025 J jnl
MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors.
CoRR
Dean You, Jieyu Jiang, Xiaoxuan Wang, Yushu Du, Zhihang Tan, Wenbo Xu, Hui Wang, Jiapeng Guan, Zhenyuan Wang, Ran Wei, Shuai Zhao, Zhe Jiang
2025 J jnl
MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors.
ACM Trans. Embed. Comput. Syst.
Dean You, Jieyu Jiang, Xiaoxuan Wang, Yushu Du, Zhihang Tan, Wenbo Xu, Hui Wang, Jiapeng Guan, Ran Wei, Shuai Zhao, Zhe Jiang
2025 J jnl
Multi-Path Bound for Parallel Tasks With Conditional Branches.
IEEE Trans. Computers
Qingqiang He, Nan Guan, Zhe Jiang, Mingsong Lv
2025 A* conf
NVR: Vector Runahead on NPUs for Sparse Memory Access.
DAC
Hui Wang, Zhengpeng Zhao, Jing Wang, Yushu Du, Yuan Cheng, Bing Guo, He Xiao, Chenhao Ma, Xiaomeng Han, Dean You, Jiapeng Guan, Ran Wei, Dawei Yang, Zhe Jiang
2025 J jnl
NVR: Vector Runahead on NPUs for Sparse Memory Access.
CoRR
Hui Wang, Zhengpeng Zhao, Jing Wang, Yushu Du, Yuan Cheng, Bing Guo, He Xiao, Chenhao Ma, Xiaomeng Han, Dean You, Jiapeng Guan, Ran Wei, Dawei Yang, Zhe Jiang
2025 A* conf
OSTQuant: Refining Large Language Model Quantization with Orthogonal and Scaling Transformations for Better Distribution Fitting.
ICLR
Xing Hu, Yuan Cheng, Dawei Yang, Zhixuan Chen, Zukang Xu, Jiangyong Yu, Chen Xu, Zhihang Yuan, Zhe Jiang, Sifan Zhou
2025 J jnl
OstQuant: Refining Large Language Model Quantization with Orthogonal and Scaling Transformations for Better Distribution Fitting.
CoRR
Xing Hu, Yuan Cheng, Dawei Yang, Zukang Xu, Zhihang Yuan, Jiangyong Yu, Chen Xu, Zhe Jiang, Sifan Zhou
2025 A* conf
Pushing the Limits of BFP on Narrow Precision LLM Inference.
AAAI
Hui Wang, Yuan Cheng, Xiaomeng Han, Zhengpeng Zhao, Dawei Yang, Zhe Jiang
2025 J jnl
Pushing the Limits of BFP on Narrow Precision LLM Inference.
CoRR
Hui Wang, Yuan Cheng, Xiaomeng Han, Zhengpeng Zhao, Dawei Yang, Zhe Jiang
2025 J jnl
Re-thinking Memory-Bound Limitations in CGRAs.
CoRR
Xiangfeng Liu, Zhe Jiang, Anzhen Zhu, Xiaomeng Han, Mingsong Lyu, Qingxu Deng, Nan Guan
2025 J jnl
Re-thinking Memory-Bound Limitations in CGRAs.
ACM Trans. Embed. Comput. Syst.
Xiangfeng Liu, Zhe Jiang, Anzhen Zhu, Xiaomeng Han, Mingsong Lyu, Qingxu Deng, Nan Guan
2025 A* conf
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection.
DAC
Juxin Niu, Xiangfeng Liu, Dan Niu, Xi Wang, Zhe Jiang, Nan Guan
2025 J jnl
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection.
CoRR
Juxin Niu, Xiangfeng Liu, Dan Niu, Xi Wang, Zhe Jiang, Nan Guan
2025 A conf
Response Time Analysis for Probabilistic Dag Tasks in Multicore Real-Time Systems.
RTSS
Shuai Zhao, Yiyang Gao, Zhiyang Lin, Boyang Li, Xinwei Fang, Zhe Jiang, Nan Guan
2025 J jnl
Thetis-lathe: Guidance on Reducing Residual Safety Obstacle in System Software from Rust Source Codes.
ACM Trans. Embed. Comput. Syst.
Renshuang Jiang, Pan Dong, Yan Ding, Ran Wei, Zhe Jiang
2025 A* conf
UVLLM: An Automated Universal RTL Verification Framework using LLMs.
DAC
Yuchen Hu, Junhao Ye, Ke Xu, Jialin Sun, Shiyue Zhang, Xinyao Jiao, Dingrong Pan, Jie Zhou, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang
2025 A* conf
Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors.
DAC
Renshuang Jiang, Pan Dong, Zhenling Duan, Yu Shi, XiaoXiang Fang, Yan Ding, Jun Ma, Shuai Zhao, Zhe Jiang
2025 J jnl
Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors.
CoRR
Renshuang Jiang, Pan Dong, Zhenling Duan, Yu Shi, XiaoXiang Fang, Yan Ding, Jun Ma, Shuai Zhao, Zhe Jiang
2025 J jnl
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction.
CoRR
Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, Zhe Jiang
2025 J jnl
VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs.
CoRR
Juxin Niu, Yuxin Du, Dan Niu, Xi Wang, Zhe Jiang, Nan Guan
2024 A* conf
A Cache/Algorithm Co-design for Parallel Real-Time Systems with Data Dependency on Multi/Many-core System-on-Chips.
DAC
Zhe Jiang, Shuai Zhao, Ran Wei, Yiyang Gao, Jing Li
2024 — conf
Adaptive Optimisation of PyTorch Memory Pools for DNNs.
PRICAI (1)
Leilei Li, Jun Luo, Pan Dong, XiaoXiang Fang, Axin Yu, Zhe Jiang
2024 J jnl
An efficient multi-task learning CNN for driver attention monitoring.
J. Syst. Archit.
Dawei Yang, Yan Wang, Ran Wei, Jiapeng Guan, Xiaohua Huang, Wei Cai, Zhe Jiang
2024 J jnl
Automated Model-Based Assurance Case Management Using Constrained Natural Language.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ran Wei, Zhe Jiang, Haitao Mei, Konstantinos Barmpis, Simon Foster, Tim Kelly, Yan Zhuang
2024 J jnl
DECISIVE: Designing Critical Systems With Iterative Automated Safety Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ran Wei, Zhe Jiang, Xiaoran Guo, Ruizhe Yang, Haitao Mei, Athanasios Zolotas, Tim Kelly
2024 J jnl
Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness.
CoRR
Zhe Jiang, Shuai Zhao, Ran Wei, Xin Si, Gang Chen, Nan Guan
2024 J jnl
Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs.
IEEE Trans. Parallel Distributed Syst.
Zhe Jiang, Kecheng Yang, Nathan Fisher, Nan Guan, Neil C. Audsley, Zheng Dong
2024 J jnl
Large Language Model for Verilog Generation with Golden Code Feedback.
CoRR
Ning Wang, Bingkun Yao, Jie Zhou, Xi Wang, Zhe Jiang, Nan Guan
2024 J jnl
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog.
CoRR
Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan
2024 A conf
MEIC: Re-thinking RTL Debug Automation using LLMs.
ICCAD
Ke Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang
2024 J jnl
MEIC: Re-thinking RTL Debug Automation using LLMs.
CoRR
Ke Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang
2024 A conf
MESC: Re-thinking Algorithmic Priority and/or Criticality Inversions for Heterogeneous MCSs.
RTSS
Jiapeng Guan, Ran Wei, Dean You, Yingquan Wang, Ruizhe Yang, Hui Wang, Zhe Jiang
2024 J jnl
MESC: Re-thinking Algorithmic Priority and/or Criticality Inversions for Heterogeneous MCSs.
CoRR
Jiapeng Guan, Ran Wei, Dean You, Yingquan Wang, Ruizhe Yang, Hui Wang, Zhe Jiang
2024 — conf
Make Each Iteration Count.
ACM TUR-C
Yuchen Hu, Ke Xu, Jialin Sun, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang
2024 J jnl
On the degree of parallelism for parallel real-time tasks.
J. Syst. Archit.
Qingqiang He, Nan Guan, Zhe Jiang, Mingsong Lv
2024 — conf
Optimization of NUMA Aware DNN Computing System.
ICIC (4)
XiaoXiang Fang, Pan Dong, Jun Luo, Leilei Li, Yan Ding, Zhe Jiang
2024 J jnl
Post-training quantization for re-parameterization via coarse & fine weight splitting.
J. Syst. Archit.
Dawei Yang, Ning He, Xing Hu, Zhihang Yuan, Jiangyong Yu, Chen Xu, Zhe Jiang
2024 A conf
ROTA-I/O: Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness.
RTSS
Zhe Jiang, Shuai Zhao, Ran Wei, Xin Si, Gang Chen, Nan Guan
2024 J jnl
Towards an Extensible Model-Based Digital Twin Framework for Space Launch Vehicles.
CoRR
Ran Wei, Ruizhe Yang, Shijun Liu, Chongsheng Fan, Rong Zhou, Zekun Wu, Haochi Wang, Yifan Cai, Zhe Jiang
2024 J jnl
Towards an extensible model-based digital twin framework for space launch vehicles.
J. Ind. Inf. Integr.
Ran Wei, Ruizhe Yang, Shijun Liu, Chongsheng Fan, Rong Zhou, Zekun Wu, Haochi Wang, Yifan Cai, Zhe Jiang
2024 J jnl
UVLLM: An Automated Universal RTL Verification Framework using LLMs.
CoRR
Yuchen Hu, Junhao Ye, Ke Xu, Jialin Sun, Shiyue Zhang, Xinyao Jiao, Dingrong Pan, Jie Zhou, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang
2023 J jnl
A High-Resilience Imprecise Computing Architecture for Mixed-Criticality Systems.
IEEE Trans. Computers
Zhe Jiang, Xiaotian Dai, Alan Burns, Neil C. Audsley, Zonghua Gu, Ian Gray
2023 J jnl
AXI-IC$^{\mathrm{ RT}}$ RT : Towards a Real-Time AXI-Interconnect for Highly Integrated SoCs.
IEEE Trans. Computers
Zhe Jiang, Kecheng Yang, Nathan Fisher, Ian Gray, Neil C. Audsley, Zheng Dong
2023 A* conf
BlueFace: Integrating an Accelerator into the Core's Pipeline through Algorithm-Interface Co-Design for Real-Time SoCs.
DAC
Zhe Jiang, Nathan Fisher, Nan Guan, Zheng Dong
2023 — conf
Many-Core Real-Time Network-on-Chip I/O Systems for Reducing Contention and Enhancing Predictability.
CPS-IoT Week Workshops
Zhe Jiang, Xiaotian Dai, Shuai Zhao, Ran Wei, Ian Gray
2023 J jnl
NPRC-I/O: An NoC-Based Real-Time I/O System With Reduced Contention and Enhanced Predictability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhe Jiang, Xiaotian Dai, Ran Wei, Ian Gray, Zonghua Gu, Qingling Zhao, Shuai Zhao
2023 J jnl
Post-Training Quantization for Re-parameterization via Coarse & Fine Weight Splitting.
CoRR
Dawei Yang, Ning He, Xing Hu, Zhihang Yuan, Jiangyong Yu, Chen Xu, Zhe Jiang
2023 J jnl
Towards Hard Real-Time and Energy-Efficient Virtualization for Many-Core Embedded Systems.
IEEE Trans. Computers
Zhe Jiang, Kecheng Yang, Yunfeng Ma, Nathan Fisher, Neil C. Audsley, Zheng Dong
2022 A* conf
BlueScale: a scalable memory architecture for predictable real-time computing on highly integrated SoCs.
DAC
Zhe Jiang, Kecheng Yang, Neil C. Audsley, Nathan Fisher, Weisong Shi, Zheng Dong
2022 J jnl
BlueVisor: Time-Predictable Hardware Hypervisor for Many-Core Embedded Systems.
IEEE Trans. Computers
Zhe Jiang, Ran Wei, Pan Dong, Yan Zhuang, Neil C. Audsley, Ian Gray
2022 J jnl
Bridging the Pragmatic Gaps for Mixed-Criticality Systems in the Automotive Industry.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhe Jiang, Shuai Zhao, Ran Wei, Dawei Yang, Richard Paterson, Nan Guan, Yan Zhuang, Neil C. Audsley
2022 A* conf
Designing critical systems with iterative automated safety analysis.
DAC
Ran Wei, Zhe Jiang, Xiaoran Guo, Haitao Mei, Athanasios Zolotas, Tim Kelly
2022 J jnl
PSpSys: A time-predictable mixed-criticality system architecture based on ARM TrustZone.
J. Syst. Archit.
Zhe Jiang, Pan Dong, Ran Wei, Qingling Zhao, Yankai Wang, Dizhong Zhu, Yan Zhuang, Neil C. Audsley
2022 J jnl
Schedulability analysis and stack size minimization for adaptive mixed criticality scheduling with semi-Clairvoyance and preemption thresholds.
J. Syst. Archit.
Qingling Zhao, Mengfei Qu, Bo Huang, Zhe Jiang, Haibo Zeng
2022 J jnl
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhe Jiang, Xiaotian Dai, Pan Dong, Ran Wei, Dawei Yang, Neil C. Audsley, Nan Guan
2022 J jnl
Towards an energy-efficient quarter-clairvoyant mixed-criticality system.
J. Syst. Archit.
Zhe Jiang, Kecheng Yang, Nathan Fisher, Neil C. Audsley, Zheng Dong
2021 Misc conf
Adaptable Ensemble Distillation.
ICASSP
Yankai Wang, Dawei Yang, Wei Zhang, Zhe Jiang, Wenqiang Zhang
2021 A conf
Brief Industry Paper: AXI-Interconnect
RTAS
Zhe Jiang, Neil C. Audsley, Dayu Shill, Kecheng Yang, Nathan Fisher, Zheng Dong
2021 A conf
HIART-MCS: High Resilience and Approximated Computing Architecture for Imprecise Mixed-Criticality Systems.
RTSS
Zhe Jiang, Xiaotian Dai, Neil C. Audsley
2021 A* conf
I/O-GUARD: Hardware/Software Co-Design for I/O Virtualization with Guaranteed Real-time Performance.
DAC
Zhe Jiang, Kecheng Yang, Yunfeng Ma, Nathan Fisher, Neil C. Audsley, Zheng Dong
2021 B conf
Work-in-Progress: a static partition for shared cache in mixed-time-sensitive system with balanced performance.
RTCSA
Pan Yang, Pan Dong, Zhe Jiang, Jintao Xia, Yan Ding
2020 Misc conf
All In One Network for Driver Attention Monitoring.
ICASSP
Dawei Yang, Xinlei Li, Xiaotian Dai, Rui Zhang, Lizhe Qi, Wenqiang Zhang, Zhe Jiang
2020 J jnl
Build real-time communication for hybrid dual-OS system.
J. Syst. Archit.
Pan Dong, Zhe Jiang, Alan Burns, Yan Ding, Jun Ma
2020 A conf
Pythia-MCS: Enabling Quarter-Clairvoyance in I/O-Driven Mixed-Criticality Systems.
RTSS
Zhe Jiang, Kecheng Yang, Nathan Fisher, Neil C. Audsley, Zheng Dong
2020 C conf
Re-Thinking Mixed-Criticality Architecture for Automotive Industry.
ICCD
Zhe Jiang, Shuai Zhao, Pan Dong, Dawei Yang, Ran Wei, Nan Guan, Neil C. Audsley
2020 A* conf
Timing-Accurate General-Purpose I/O for Multi- and Many-Core Systems: Scheduling and Hardware Support.
DAC
Shuai Zhao, Zhe Jiang, Xiaotian Dai, Iain Bate, Ibrahim Habli, Wanli Chang
2019 J jnl
BlueIO: A Scalable Real-Time Hardware I/O Virtualization System for Many-core Embedded Systems.
ACM Trans. Embed. Comput. Syst.
Zhe Jiang, Neil C. Audsley, Pan Dong
2019 A conf
MCS-IOV: Real-Time I/O Virtualization for Mixed-Criticality Systems.
RTSS
Zhe Jiang, Neil C. Audsley, Pan Dong, Nan Guan, Xiaotian Dai, Lifeng Wei
2019 A conf
Work-in-Progress: Real-Time RPC for Hybrid Dual-OS System.
RTSS
Pan Dong, Zhe Jiang, Alan Burns, Yan Ding, Jun Ma
2018 A conf
BlueVisor: A Scalable Real-Time Hardware Hypervisor for Many-Core Embedded Systems.
RTAS
Zhe Jiang, Neil C. Audsley, Pan Dong
2018 — —
Real-time I/O system for many-core embedded systems.
Zhe Jiang
2018 B conf
TZDKS: A New TrustZone-Based Dual-Criticality System with Balanced Performance.
RTCSA
Pan Dong, Alan Burns, Zhe Jiang, Xiangke Liao
2017 A conf
GPIOCP: Timing-accurate general purpose I/O controller for many-core real-time systems.
DATE
Zhe Jiang, Neil C. Audsley
2017 B conf
VCDC: The Virtualized Complicated Device Controller.
ECRTS
Zhe Jiang, Neil C. Audsley