Zhanping Chen

29 papers A* 3A 4Journal 14Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Bandgap Diode-Based Voltage Band Detection Circuit With Fast Response Time and Low Vmin on Intel 4 Logic Technology.
IEEE Solid State Circuits Lett.
Kedar Bhatt, Stafford Hutchins, Atresh Sanne, Mohammad M. Hasan, Zhanping Chen, Jaydeep P. Kulkarni
2022 — conf
A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology.
VLSI Technology and Circuits
Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni
2017 J jnl
A 0.9-μm
IEEE J. Solid State Circuits
Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Salil Manohar Rajarshi, Lei Jiang, Uddalak Bhattacharya
2016 — conf
A 0.9um
VLSI Circuits
Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang
2016 J jnl
A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits
Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang
2015 — conf
Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process.
VLSIC
Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang
2010 J jnl
A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m
IEEE J. Solid State Circuits
Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, Brian Pedersen, Kevin Zhang
2009 J jnl
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology.
IEEE J. Solid State Circuits
Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr
2008 J jnl
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.
IEEE J. Solid State Circuits
Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr
2008 — conf
A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology.
ISSCC
Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr
2006 J jnl
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply.
IEEE J. Solid State Circuits
Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr
2005 J jnl
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction.
IEEE J. Solid State Circuits
Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr
2002 — conf
IDDQ Testing for Deep Submicron ICs: Challenges and Solutions.
LATW
Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
2002 J jnl
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions.
IEEE Des. Test Comput.
Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
2002 J jnl
Vertically integrated SOI circuits for low-power and high-performance applications.
IEEE Trans. Very Large Scale Integr. Syst.
Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes
2001 A conf
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.
ISLPED
James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
2001 J jnl
On effective I
IEEE Trans. Very Large Scale Integr. Syst.
Zhanping Chen, Liqiong Wei, Kaushik Roy
2000 J jnl
Estimation of power dissipation using a novel power macromodelingtechnique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
2000 — conf
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.
ISQED
Zhanping Chen, Liqiong Wei, Kaushik Roy
1999 J jnl
Design and optimization of dual-threshold circuits for low-voltage low-power applications.
IEEE Trans. Very Large Scale Integr. Syst.
Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
1999 A* conf
Mixed-
DAC
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
1999 — conf
Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.
ISCAS (1)
Kaushik Roy, Liqiong Wei, Zhanping Chen
1998 A* conf
A Power Macromodeling Technique Based on Power Sensitivity.
DAC
Zhanping Chen, Kaushik Roy
1998 A* conf
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.
DAC
Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De
1998 J jnl
Efficient statistical approach to estimate power considering uncertain properties of primary inputs.
IEEE Trans. Very Large Scale Integr. Syst.
Zhanping Chen, Kaushik Roy, Tan-Li Chou
1998 — conf
Estimation of average switching power under accurate modeling of signal correlations.
CICC
Zhanping Chen, Kaushik Roy, Yibin Ye
1998 A conf
Estimation of power sensitivity in sequential circuits with power macromodeling application.
ICCAD
Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
1998 A conf
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.
ISLPED
Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy
1997 A conf
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.
ICCAD
Zhanping Chen, Kaushik Roy, Tan-Li Chou