Zhangcai Huang

27 papers C 7Journal 17Unranked 3
YearRankTypeTitle / Venue / Authors
2014 J jnl
An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Li Ding, Zhangcai Huang, Atsushi Kurokawa, Jing Wang, Yasuaki Inoue
2013 C conf
An analytical model of the overshooting effect for multiple-input gates in nanometer technologies.
ISCAS
Li Ding, Jing Wang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue
2012 C conf
A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model.
ISCAS
Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue
2012 J jnl
Modeling the Overshooting Effect of Multi-Input gate in Nanometer Technologies.
J. Circuits Syst. Comput.
Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue
2011 J jnl
A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue
2011 C conf
A sub-100nA power management system for wireless structure health monitoring applications.
ISCAS
Zhangcai Huang, Yasuaki Inoue
2010 C conf
A CMOS Sub-l-V nanopower current and voltage reference with leakage compensation.
ISCAS
Zhangcai Huang, Qin Luo, Yasuaki Inoue
2010 C conf
A low voltage CMOS rectifier for wirelessly powered devices.
ISCAS
Qiang Li, Renyuan Zhang, Zhangcai Huang, Yasuaki Inoue
2010 J jnl
Memristor Model for SPICE.
IEICE Trans. Electron.
Xuliang Zhang, Zhangcai Huang, Juebang Yu
2010 J jnl
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue
2009 J jnl
A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback.
IEICE Trans. Electron.
Zhangcai Huang, Minglu Jiang, Yasuaki Inoue
2009 J jnl
Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue
2007 J jnl
A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jun Pan, Yasuaki Inoue, Zheng Liang, Zhangcai Huang, Weilun Huang
2007 J jnl
An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hong Yu, Yasuaki Inoue, Kazutoshi Sako, Xiaochuan Hu, Zhangcai Huang
2007 J jnl
Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Zhangcai Huang, Yasuaki Inoue, Hong Yu, Jun Pan, Yun Yang, Quan Zhang, Shuai Fang
2007 — conf
Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies.
ASP-DAC
Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue
2006 — conf
A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback.
APCCAS
Zhangcai Huang, Yasuaki Inoue, Hong Yu, Quan Zhang
2006 J jnl
An Effective Pseudo-Transient Algorithm for Finding Dc Solutions of Nonlinear Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang
2006 C conf
An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits.
ISCAS
Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang
2006 C conf
Behavioral macromodeling of analog LSI implementation for automobile intake system.
ISCAS
Zhangcai Huang, Yasuaki Inoue, Quan Zhang, Yuehu Zhou, Long Xie, Harutoshi Ogai
2006 J jnl
Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue
2006 J jnl
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda
2006 J jnl
Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue
2005 J jnl
A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao
2005 — conf
Effective capacitance for gate delay with RC loads.
ISCAS (3)
Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue
2005 J jnl
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue
2005 J jnl
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda