Zhang Zhang

52 papers C 1Journal 45Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 10-Bit 120-MS/s SAR ADC With Intermediate-Voltage Dynamic Comparator and Calibration Scheme for Quantitative Decoupling.
Int. J. Circuit Theory Appl.
Xuanhe Zhang, Huijuan Li, Yuchen Sun, Aoyun Sun, Zhang Zhang
2026 J jnl
A 109-dB SFDR Continuous-Time Delta-Sigma Modulator for Audio Using Bi-Directional Advancing Data Weighted Averaging.
IEEE Trans. Circuits Syst. II Express Briefs
Aoyun Sun, Lingling Wei, Hong Yang, Gang Liu, Zhang Zhang
2026 J jnl
A differential in-memory computing 12T SRAM macro with enhanced flexibility and reliability for XNOR-network.
Integr.
Dekai Sun, Zhang Zhang, Wenyan Liu, Hongbin Yang, Yi Lu, Yonghong Zeng, Biao Zhang, Lianjie Lu
2026 J jnl
Design of image encryption and compression scheme compatible with JPEG XS based on spatial scrambling.
Microelectron. J.
Yizhong Yang, Junhao Zheng, Xiaodie Zhang, Zhang Zhang
2025 J jnl
A 15.4 nW, 59 ppm/∘C CMOS voltage reference circuit with process and temperature compensation.
Microelectron. J.
Annan Wang, Yuchen Sun, Zhang Zhang
2025 J jnl
A Lightweight Authenticated Encryption Algorithm Based on Compact CLEFIA Block Cipher.
J. Circuits Syst. Comput.
MeiYu Liang, Tao Ji, Yin Yuan, Xin Cheng, Zhang Zhang, Lixiang Ma
2025 J jnl
A class-AB rail-to-rail operational amplifier with wide supply voltage and high gain.
Microelectron. J.
Sikai Chen, Peng Zhang, Lumiao Zhang, Zhang Zhang
2025 J jnl
An oscillator replica bitline technique for suppressing timing variation of SRAM sense amplifiers.
IEICE Electron. Express
Dekai Sun, Zhihao Chen, Sikai Chen, Zhang Zhang
2025 J jnl
Reconfigurable 10T SRAM for Energy-Efficient CAM Operation and In-Memory Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Zhang Zhang, Zhihao Chen, Jiedong Wang, Guangjun Xie, Gang Liu
2024 C conf
A 10T SRAM with Two Read and Write Modes across Row and Column for CAM Operation and Computing In-Memory.
ISCAS
Zhang Zhang, Zhihao Chen, Sikai Chen, Guangjun Xie, Jianmin Zeng, Gang Liu
2024 J jnl
A gate-tunable memristor emulator for motion detection.
Int. J. Circuit Theory Appl.
Zhang Zhang, Yongbo Ma, Gang Shi, Chao Li, Gang Liu
2024 J jnl
Cascaded refinement residual attention network for image outpainting.
Multim. Syst.
Yizhong Yang, Shanshan Yao, Changjiang Liu, Zhang Zhang, Guangjun Xie
2024 J jnl
Memristor-Based Neural Network Circuit of Associative Memory With Occasion Setting.
IEEE Trans. Cogn. Dev. Syst.
Juntao Han, Xin Cheng, Guangjun Xie, Junwei Sun, Gang Liu, Zhang Zhang
2024 J jnl
Voltage-Resistance-Adaptive MPPT Circuit for Energy Harvesting.
IEEE Des. Test
Zhang Zhang, Annan Wang, Hongtao Ren, Guangjun Xie, Xin Cheng
2023 J jnl
A multi-scale feature fusion spatial-channel attention model for background subtraction.
Multim. Syst.
Yizhong Yang, Tingting Xia, Dajin Li, Zhang Zhang, Guangjun Xie
2023 J jnl
A multi-scale inputs and labels model for background subtraction.
Signal Image Video Process.
Yizhong Yang, Dajin Li, Xiang Li, Zhang Zhang, Guangjun Xie
2023 J jnl
An FPGA-based memristor emulator for artificial neural network.
Microelectron. J.
Zhang Zhang, Chao Li, Weiqi Zhang, Jing Zhou, Gang Liu
2023 J jnl
Cascaded deep residual learning network for single image dehazing.
Multim. Syst.
Yizhong Yang, Ce Hou, Haixia Huang, Zhang Zhang, Guangjun Xie
2023 J jnl
Lightweight and flexible hardware implementation of authenticated encryption algorithm SIMON-Galois/Counter Mode.
Int. J. Circuit Theory Appl.
Xin Cheng, Yixuan Xu, Kefan Wang, Yongqiang Zhang, Bin Li, Zhang Zhang
2022 J jnl
Gate-Controlled Memristor FPGA Model for Quantified Neural Network.
IEEE Trans. Circuits Syst. II Express Briefs
Zhang Zhang, Ao Xu, Chao Li, Yadong Wei, Zhiheng Ge, Xin Cheng, Gang Liu
2022 J jnl
MSE-Net: generative image inpainting with multi-scale encoder.
Vis. Comput.
Yizhong Yang, Zhihang Cheng, Haotian Yu, Yongqiang Zhang, Xin Cheng, Zhang Zhang, Guangjun Xie
2022 J jnl
Mathematical analysis and circuit emulator design of the three-valued memristor.
Integr.
Zhang Zhang, Ao Xu, Chao Li, Gang Liu, Xin Cheng
2022 J jnl
Reconfigurable multivalued memristor FPGA model for digital recognition.
Int. J. Circuit Theory Appl.
Zhang Zhang, Ao Xu, Hongtao Ren, Gang Liu, Xin Cheng
2022 J jnl
STPNet: A Spatial-Temporal Propagation Network for Background Subtraction.
IEEE Trans. Circuits Syst. Video Technol.
Yizhong Yang, Jiahao Ruan, Yongqiang Zhang, Xin Cheng, Zhang Zhang, Guangjun Xie
2021 — conf
A Feedback Architecture of High Speed True Random Number Generator based on Ring Oscillator.
A-SSCC
Xin Cheng, Haowen Zhu, Xinyi Xing, Yunfeng Zhang, Yongqiang Zhang, Guangjun Xie, Zhang Zhang
2021 J jnl
A high-resolution hybrid digital pulse width modulator with dual-edge-triggered flip-flops and hardware compensation.
Int. J. Circuit Theory Appl.
Xin Cheng, Bin Li, Haowen Zhu, Yongqiang Zhang, Zhang Zhang
2021 J jnl
A novel control circuit for piezoelectric energy harvesting.
Microelectron. J.
Zhang Zhang, Zechen Tang, Zhang Yunfeng, Xin Cheng, Guangjun Xie
2021 J jnl
A reconfigurable and compact hardware architecture of CLEFIA block cipher with multi-configuration.
Microelectron. J.
Xin Cheng, Haowen Zhu, Yixuan Xu, Yongqiang Zhang, Hao Xiao, Zhang Zhang
2021 J jnl
An output capacitor-less low-dropout regulator with wide load capacitance and current ranges.
Int. J. Circuit Theory Appl.
Zhang Zhang, Shu Xu, Hongyuan Wu, Guangjun Xie, Xin Cheng
2021 J jnl
Using correction parameters to improve real-time video interpolation in low-cost VLSI implementation.
Microelectron. J.
Haowei Guan, Zhang Zhang, Xin Cheng, Yizhong Yang, Guangjun Xie
2020 J jnl
A High Resolution DPWM Based on Synchronous Phase-Shifted Circuit and Delay Line.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin Cheng, Wanjing Shao, Lixin Xu, Yongqiang Zhang, Guangjun Xie, Zhang Zhang
2020 J jnl
Algorithm-Hardware Co-Design of Real-Time Edge Detection for Deep-Space Autonomous Optical Navigation.
IEICE Trans. Inf. Syst.
Hao Xiao, Yanming Fan, Fen Ge, Zhang Zhang, Xin Cheng
2020 J jnl
CFE: a convenient, flexible, and efficient clocking scheme for quantum-dot cellular automata.
IET Circuits Devices Syst.
Feifei Deng, Guangjun Xie, Xin Cheng, Zhang Zhang, Yongqiang Zhang
2020 J jnl
DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing.
IEICE Electron. Express
Jianmin Zeng, Zhang Zhang, Runhao Chen, Shiyue Liang, Tianlin Cao, Zhiyi Yu, Xin Cheng, Guangjun Xie
2020 J jnl
High frequency and high efficiency DC-DC converter with sensorless adaptive-sizing technique.
IEICE Electron. Express
Xin Cheng, Wanjing Shao, Yongqiang Zhang, Jianmin Zeng, Zhang Zhang
2019 J jnl
A 24-bit sigma-delta ADC with configurable chopping scheme.
IEICE Electron. Express
Li Li, Xu Cheng, Zhang Zhang, Jianmin Zeng, Xiaoyang Zeng
2019 — conf
A 30MHz Delay-Line-Based Buck Converter with 5.7%-94.8% Switching Duty Cycle.
APCCAS
Zhang Zhang, Shu Xu, Fangzhou Yao, Guangjun Xie, Xin Cheng
2019 — conf
A Fast and Accurate Edge Detection Algorithm for Real-Time Deep-Space Autonomous Optical Navigation.
IDAACS
Hao Xiao, Yanming Fan, Zhang Zhang, Xin Cheng
2019 — conf
A Single-Input Multi-Output Piezoelectric Energy Harvesting System Combining with P-SSHI and Cold Startup Circuit.
APCCAS
Xin Cheng, Bo Cheng, Zechen Tang, Yongqiang Zhang, Zhang Zhang
2019 J jnl
Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata.
J. Circuits Syst. Comput.
Haotian Chen, Hongjun Lv, Zhang Zhang, Xin Cheng, Guangjun Xie
2018 J jnl
A 15 W wireless power receiver with an improved full-wave synchronous rectifier.
IEICE Electron. Express
Chubin Wu, Guangjun Xie, Zhang Zhang, Xin Cheng, Tairan Fei, Jianmin Zeng, Xiaoyang Zeng
2018 J jnl
A Qi compatible wireless power receiver with integrated full-wave synchronous rectifier.
Sci. China Inf. Sci.
Chubin Wu, Zhang Zhang, Jianmin Zeng, Xin Cheng, Guangjun Xie
2018 J jnl
Countering power analysis attacks by exploiting characteristics of multicore processors.
IEICE Electron. Express
Jianwei Yang, Fan Dai, Jielin Wang, Jianmin Zeng, Zhang Zhang, Jun Han, Xiaoyang Zeng
2018 — conf
Study of High Voltage Deep Brain Stimulation.
APCCAS
Zhang Zhang, Lingling Wei, Xiaojuan Zhou, Taolue Zhu, Guangjun Xie, Xin Cheng
2017 J jnl
A multi-core-based heterogeneous parallel turbo decoder.
IEICE Electron. Express
Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu
2017 J jnl
An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator.
J. Circuits Syst. Comput.
Xin Cheng, Hongyu Liang, Longjie Du, Zhang Zhang, Maoxiang Yi, Guangjun Xie
2015 J jnl
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu
2014 J jnl
A 16-Core Processor With Shared-Memory and Message-Passing Communications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng
2014 J jnl
Fast-Settling Feedforward Automatic Gain Control Based on a New Gain Control Approach.
IEEE Trans. Circuits Syst. II Express Briefs
Xin Cheng, Guangjun Xie, Zhang Zhang, Yizhong Yang
2013 J jnl
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Pengjun Wang, Yuejun Zhang, Jun Han, Zhiyi Yu, Yibo Fan, Zhang Zhang
2012 J jnl
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.
IEICE Electron. Express
Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng
2011 — conf
A low power 1.0 GHz VCO in 65nm-CMOS LP-process.
ASICON
Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng