Zeynep Toprak Deniz

33 papers A 1C 1Journal 11Unranked 20
YearRankTypeTitle / Venue / Authors
2024 — conf
A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1\mathrm{V}_{\text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS.
VLSI Technology and Circuits
Zeynep Toprak Deniz, Timothy O. Dickson, Martin Cochet, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Matthias Brändli, Thomas Morf, Michael P. Beakes, Mounir Meghelli
2024 — conf
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration.
CICC
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli
2023 J jnl
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2022 — conf
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.
VLSI Technology and Circuits
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2022 — conf
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.
VLSI Technology and Circuits
Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2021 — conf
SE4: ICs in PandemICs.
ISSCC
Negar Reiskarimian, Zeynep Toprak Deniz, Ulkuhan Guler, Kathy Wilcox, Alice Wang, Jane Gu, Yaoyao Jia, Alicia Klinefelter, Rikky Muller, Farhana Sheikh, Yildiz Sinangil, Trudy Stetzler, Vivienne Sze, Rabia Tugce Yazicigil, Deeksha Lal, Dina El-Damak
2020 J jnl
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS.
IEEE J. Solid State Circuits
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
2020 J jnl
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS.
IEEE J. Solid State Circuits
Miguel E. Perez, Michael A. Sperling, John F. Bulzacchelli, Zeynep Toprak Deniz, Timothy E. Diemoz
2020 J jnl
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
2019 — conf
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS.
ISSCC
Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli
2019 — conf
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS.
CICC
Miguel E. Perez, Michael A. Sperling, Timothy E. Diemoz, John F. Bulzacchelli, Zeynep Toprak Deniz
2018 J jnl
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS.
IEEE J. Solid State Circuits
Jonathan E. Proesel, Zeynep Toprak Deniz, Alessandro Cevrero, Ilter Özkaya, Seongwon Kim, Daniel M. Kuchta, Sungjae Lee, Sergey V. Rylov, Herschel A. Ainspan, Timothy O. Dickson, John F. Bulzacchelli, Mounir Meghelli
2016 — conf
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.
ISSCC
Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli
2016 J jnl
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman
2015 — conf
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
CICC
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman
2015 J jnl
IBM POWER8 circuit design and energy optimization.
IBM J. Res. Dev.
Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny
2015 J jnl
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits
Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban
2014 — conf
5.1 POWER8
ISSCC
Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler
2014 — conf
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8
ISSCC
Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich
2014 — conf
The POWER8
ICICDT
Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor
2012 — conf
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS.
CICC
Jean-Olivier Plouchart, Mihai A. T. Sanduleanu, Zeynep Toprak Deniz, Troy J. Beukema, Scott K. Reynolds, Benjamin D. Parker, Michael P. Beakes, José A. Tierno, Daniel J. Friedman
2012 J jnl
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage.
IEEE J. Solid State Circuits
John F. Bulzacchelli, Zeynep Toprak Deniz, Todd M. Rasmus, Joseph A. Iadanza, William L. Bucossi, Seongwon Kim, Rafael Blanco, Carrie E. Cox, Mohak Chhabra, Christopher D. LeBlanc, Christian L. Trudeau, Daniel J. Friedman
2012 A conf
Root cause identification of an hard-to-find on-chip power supply coupling fail.
ITC
Franco Stellari, Thomas Cowell, Peilin Song, Michael Sorna, Zeynep Toprak Deniz, John F. Bulzacchelli, Nandita A. Mitra
2009 — conf
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
ISSCC
John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman
2009 — conf
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
ISSCC
Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman
2009 J jnl
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Trans. Comput. Sci.
Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
2008 — conf
A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology.
APCCAS
Thomas Liechti, Armin Tajalli, Omer Can Akgun, Zeynep Toprak Deniz, Yusuf Leblebici
2007 — conf
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
ICSAMOS
Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
2007 J jnl
On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation.
IEEE J. Solid State Circuits
Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz
2006 C conf
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.
VLSI-SoC
Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz
2006 — conf
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.
VLSI-SoC (Selected Papers)
Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz
2005 — conf
Low-power current mode logic for improved DPA-resistance in embedded systems.
ISCAS (2)
Zeynep Toprak Deniz, Yusuf Leblebici
2003 — conf
Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology.
ISCAS (1)
Zeynep Toprak Deniz, Yusuf Leblebici