Zeye Liu

20 papers A* 2A 6C 2Misc 1Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2023 J jnl
Efficient Test Chip Design via Smart Computation.
ACM Trans. Design Autom. Electr. Syst.
Chenlei Fang, Qicheng Huang, Zeye Liu, Ruizhou Ding, Ronald D. Blanton
2020 A conf
High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips.
ITC
Zeye Liu, R. D. Shawn Blanton
2019 — conf
Characterization of Locked Sequential Circuits via ATPG.
ITC-Asia
Danielle Duvalsaint, Zeye Liu, Ananya Ravikumar, Ronald D. Blanton
2019 A* conf
FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference.
DAC
Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, R. D. (Shawn) Blanton
2019 J jnl
FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference.
CoRR
Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, Ronald D. Blanton
2019 C conf
IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design.
ICCD
Qicheng Huang, Chenlei Fang, Zeye Liu, Ruizhou Ding, R. D. Shawn Blanton
2019 A conf
Improving Test Chip Design Efficiency via Machine Learning.
ITC
Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton
2019 Misc conf
Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle.
VTS
Ben Niewenhuis, Balaji Ravikumar, Zeye Liu, R. D. Shawn Blanton
2019 A* conf
Regularizing Activation Distribution for Training Binarized Deep Networks.
CVPR
Ruizhou Ding, Ting-Wu Chin, Zeye Liu, Diana Marculescu
2019 J jnl
Regularizing Activation Distribution for Training Binarized Deep Networks.
CoRR
Ruizhou Ding, Ting-Wu Chin, Zeye Liu, Diana Marculescu
2018 C conf
Back-End Layout Reflection for Test Chip Design.
ICCD
Zeye Liu, Ronald D. Blanton
2018 — conf
CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation.
IEEE BigData
Abhinav Goel, Zeye Liu, Ronald D. Blanton
2018 J jnl
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks.
CoRR
Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton
2018 J jnl
Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs.
ACM Trans. Reconfigurable Technol. Syst.
Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu
2018 — conf
Quantized deep neural networks for energy efficient hardware-based inference.
ASP-DAC
Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu
2017 A conf
Front-end layout reflection for test chip design.
ITC
Zeye Liu, Phillip Fynan, Ronald D. Blanton
2017 — conf
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks.
ACM Great Lakes Symposium on VLSI
Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton
2016 A conf
Achieving 100% cell-aware coverage by design.
DATE
Zeye Liu, Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton
2016 A conf
Logic characterization vehicle design reflection via layout rewiring.
ITC
Phillip Fynan, Zeye Liu, Benjamin Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. (Shawn) Blanton
2016 A conf
Test chip design for optimal cell-aware diagnosability.
ITC
Soumya Mittal, Zeye Liu, Ben Niewenhuis, R. D. (Shawn) Blanton