Zehan Cui - RankMe

19 papers A* 2A 1B 4C 2Journal 7Unranked 3

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Neural network-based forecasting and uncertainty analysis of new power generation capacity of electric energy. Energy Inform. Xingyu Dou, Zehan Cui
2016	—	`conf`	Twin-Load: Bridging the Gap between Conventional Direct-Attached and Buffer-on-Board Memory Systems. MEMSYS Zehan Cui, Tianyue Lu, Sally A. McKee, Mingyu Chen, Haiyang Pan, Yuan Ruan
2015	J	`jnl`	Cracking Intel Sandy Bridge's Cache Hash Function. CoRR Zhipeng Wei, Zehan Cui, Mingyu Chen
2015	J	`jnl`	Twin-Load: Building a Scalable Memory System over the Non-Scalable Interface. CoRR Zehan Cui, Tianyue Lu, Haiyang Pan, Sally A. McKee, Mingyu Chen
2014	A*	`conf`	A Swap-based Cache Set Index Scheme to Leverage both Superpage and Page Coloring Optimizations. DAC Zehan Cui, Licheng Chen, Yungang Bao, Mingyu Chen
2014	J	`jnl`	BPM/BPM+: Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems. ACM Trans. Archit. Code Optim. Lei Liu, Zehan Cui, Yong Li, Yungang Bao, Mingyu Chen, Chengyong Wu
2014	B	`conf`	CMD: classification-based memory deduplication through page access characteristics. VEE Licheng Chen, Zhipeng Wei, Zehan Cui, Mingyu Chen, Haiyang Pan, Yungang Bao
2014	A	`conf`	DTail: a flexible approach to DRAM refresh management. ICS Zehan Cui, Sally A. McKee, Zhongbin Zha, Yungang Bao, Mingyu Chen
2014	A*	`conf`	Going vertical in memory management: Handling multiplicity by multi-policy. ISCA Lei Liu, Yong Li, Zehan Cui, Yungang Bao, Mingyu Chen, Chengyong Wu
2014	J	`jnl`	HMTT: A hybrid hardware/software tracing system for bridging the DRAM access trace's semantic gap. ACM Trans. Archit. Code Optim. Yongbing Huang, Licheng Chen, Zehan Cui, Yuan Ruan, Yungang Bao, Mingyu Chen, Ninghui Sun
2014	J	`jnl`	MIMS: Towards a Message Interface Based Memory System. J. Comput. Sci. Technol. Licheng Chen, Mingyu Chen, Yuan Ruan, Yongbing Huang, Zehan Cui, Tianyue Lu, Yungang Bao
2013	—	`conf`	A Study of Leveraging Memory Level Parallelism for DRAM System on Multi-core/Many-Core Architecture. TrustCom/ISPA/IUCC Licheng Chen, Yongbing Huang, Yungang Bao, Guangming Tan, Zehan Cui
2013	J	`jnl`	MIMS: Towards a Message Interface based Memory System CoRR Licheng Chen, Tianyue Lu, Yanan Wang, Mingyu Chen, Yuan Ruan, Zehan Cui, Yongbing Huang, Mingyang Chen, Jiutian Zhang, Yungang Bao
2013	C	`conf`	Scattered superpage: A case for bridging the gap between superpage and page coloring. ICCD Licheng Chen, Yanan Wang, Zehan Cui, Yongbing Huang, Yungang Bao, Mingyu Chen
2012	B	`conf`	A lightweight hybrid hardware/software approach for object-relative memory profiling. ISPASS Licheng Chen, Zehan Cui, Yungang Bao, Mingyu Chen, Yongbing Huang, Guangming Tan
2012	B	`conf`	A software memory partition approach for eliminating bank-level interference in multicore systems. PACT Lei Liu, Zehan Cui, Mingjie Xing, Yungang Bao, Mingyu Chen, Chengyong Wu
2012	C	`conf`	Evaluation and Optimization of Breadth-First Search on NUMA Cluster. CLUSTER Zehan Cui, Licheng Chen, Mingyu Chen, Yungang Bao, Yongbing Huang, Huiwei Lv
2012	B	`conf`	HaLock: hardware-assisted lock contention detection in multithreaded applications. PACT Yongbing Huang, Zehan Cui, Licheng Chen, Wenli Zhang, Yungang Bao, Mingyu Chen
2011	—	`conf`	A fine-grained component-level power measurement method. IGCC Zehan Cui, Yan Zhu, Yungang Bao, Mingyu Chen