Zdenek Vasícek

119 papers A* 2A 17B 19C 9Misc 1Journal 30Unranked 37

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Arbitrary Precision Printed Ternary Neural Networks with Holistic Evolutionary Approximation. CoRR Vojtech Mrazek, Konstantinos Balaskas, Paula Carolina Lozano Duarte, Zdenek Vasícek, Mehdi B. Tahoori, Georgios Zervakis
2025	C	`conf`	AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs. ISCAS Vojtech Mrazek, Zdenek Vasícek
2025	J	`jnl`	AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs. CoRR Vojtech Mrazek, Zdenek Vasícek
2025	—	`conf`	Efficient Scheduling of Transformer Neural Network Computation for Edge-AI Deployment. GECCO Companion David Sedlak, Jan Klhufek, Vojtech Mrazek, Zdenek Vasícek
2025	—	`conf`	TinyverseGP: Towards a Modular Cross-domain Benchmarking Framework for Genetic Programming. GECCO Companion Roman Kalkreuth, Fabrício Olivetti de França, Anja Jankovic, Marie Anastacio, Julian Dierkes, Zdenek Vasícek, Holger H. Hoos
2025	J	`jnl`	TinyverseGP: Towards a Modular Cross-domain Benchmarking Framework for Genetic Programming. CoRR Roman Kalkreuth, Fabrício Olivetti de França, Julian Dierkes, Marie Anastacio, Anja Jankovic, Zdenek Vasícek, Holger H. Hoos
2025	—	`conf`	Towards Efficient Semantic Mutation in CGP: Enhancing SOMO GECCO Companion Lukas Plevac, Zdenek Vasícek
2024	B	`conf`	Automated Synthesis of Commutative Approximate Arithmetic Operators. CEC Zdenek Vasícek
2024	A	`conf`	Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. DATE Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2024	A	`conf`	Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. ICCAD Vojtech Mrazek, Argyris Kokkinis, Panagiotis Papanikolaou, Zdenek Vasícek, Kostas Siozios, Georgios Tzimpragos, Mehdi B. Tahoori, Georgios Zervakis
2024	J	`jnl`	Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. CoRR Vojtech Mrazek, Argyris Kokkinis, Panagiotis Papanikolaou, Zdenek Vasícek, Kostas Siozios, Georgios Tzimpragos, Mehdi Baradaran Tahoori, Georgios Zervakis
2024	C	`conf`	Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. DDECS Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2024	J	`jnl`	Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. CoRR Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2023	J	`jnl`	Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Michal Pinos, Vojtech Mrazek, Filip Vaverka, Zdenek Vasícek, Lukás Sekanina
2023	A	`conf`	General Boolean Function Benchmark Suite. FOGA Roman Kalkreuth, Zdenek Vasícek, Jakub Husa, Diederick Vermetten, Furong Ye, Thomas Bäck
2023	B	`ed.`	Genetic Programming - 26th European Conference, EuroGP 2023, Held as Part of EvoStar 2023, Brno, Czech Republic, April 12-14, 2023, Proceedings EuroGP Gisele L. Pappa, Mario Giacobini, Zdenek Vasícek
2023	—	`conf`	Towards a General Boolean Function Benchmark Suite. GECCO Companion Roman Kalkreuth, Zdenek Vasícek, Jakub Husa, Diederick Vermetten, Furong Ye, Thomas Bäck
2023	A	`conf`	Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. ICCAD Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2023	J	`jnl`	autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. CoRR Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2022	—	`conf`	Delay-aware evolutionary optimization of digital circuits. ISVLSI Jitka Kocnová, Zdenek Vasícek
2022	—	`conf`	Graph-based genetic programming. GECCO Companion Roman Kalkreuth, Léo Françoso Dal Piccol Sotto, Zdenek Vasícek
2022	J	`jnl`	SagTree: Towards efficient mutation in evolutionary circuit approximation. Swarm Evol. Comput. Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2021	C	`conf`	Resynthesis of logic circuits using machine learning and reconvergent paths. DSD Jitka Kocnová, Zdenek Vasícek
2021	J	`jnl`	Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. Genet. Program. Evolvable Mach. David Hodan, Vojtech Mrazek, Zdenek Vasícek
2021	C	`conf`	Synthesis of approximate circuits for LUT-based FPGAs. DDECS Zdenek Vasícek
2020	J	`jnl`	Adaptive Verifiability-Driven Strategy for Evolutionary Approximation of Arithmetic Circuits. CoRR Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2020	J	`jnl`	Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Appl. Soft Comput. Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2020	A*	`conf`	ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. DAC Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2020	J	`jnl`	ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. CoRR Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2020	B	`conf`	Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel
2020	J	`jnl`	EA-based resynthesis: an efficient tool for optimization of digital circuits. Genet. Program. Evolvable Mach. Jitka Kocnová, Zdenek Vasícek
2020	J	`jnl`	Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. Very Large Scale Integr. Syst. Mohammad Saeed Ansari, Vojtech Mrazek, Bruce F. Cockburn, Lukás Sekanina, Zdenek Vasícek, Jie Han
2020	J	`jnl`	Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
2020	J	`jnl`	Semantically-Oriented Mutation Operator in Cartesian Genetic Programming for Evolutionary Circuit Design. CoRR David Hodan, Vojtech Mrazek, Zdenek Vasícek
2020	A	`conf`	Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. GECCO David Hodan, Vojtech Mrazek, Zdenek Vasícek
2020	A	`conf`	TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. DATE Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2020	J	`jnl`	TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. CoRR Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2020	—	`conf`	Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. AICAS Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
2020	J	`jnl`	Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. CoRR Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
2019	A	`conf`	ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. ICCAD Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
2019	J	`jnl`	ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. CoRR Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
2019	A	`conf`	Automated Circuit Approximation Method Driven by Data Distribution. DATE Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2019	J	`jnl`	Automated Circuit Approximation Method Driven by Data Distribution. CoRR Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2019	—	`ch.`	Automated Search-Based Functional Approximation for Digital Circuits. Approximate Circuits Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek
2019	C	`conf`	EA-Based Refactoring of Mapped Logic Circuits. ISCAS Jitka Kocnová, Zdenek Vasícek
2019	J	`jnl`	Formal Methods for Exact Analysis of Approximate Circuits. IEEE Access Zdenek Vasícek
2019	—	`conf`	Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits. GECCO (Companion) Jitka Kocnová, Zdenek Vasícek
2019	B	`conf`	Towards a Scalable EA-Based Optimization of Digital Circuits. EuroGP Jitka Kocnová, Zdenek Vasícek
2019	A*	`conf`	autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. DAC Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2019	J	`jnl`	autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. CoRR Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
2018	—	`conf`	ADAC: Automated Design of Approximate Circuits. CAV (1) Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2018	—	`conf`	Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. ICECS Lukás Sekanina, Vojtech Mrazek, Zdenek Vasícek
2018	—	`conf`	Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. AHS Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2018	—	`conf`	Evolutionary design of large approximate adders optimized for various error criteria. GECCO (Companion) Vojtech Mrazek, Zdenek Vasícek
2018	A	`conf`	Evolving boolean functions for fast and efficient randomness testing. GECCO Vojtech Mrazek, Marek Sýs, Zdenek Vasícek, Lukás Sekanina, Vashek Matyas
2018	J	`jnl`	Role of circuit representation in evolutionary design of energy-efficient approximate circuits. IET Comput. Digit. Tech. Vojtech Mrazek, Zdenek Vasícek, Radek Hrbacek
2018	J	`jnl`	Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. Very Large Scale Integr. Syst. Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Honglan Jiang, Jie Han
2018	Misc	`conf`	Special session: How approximate computing impacts verification, test and reliability. VTS Lukás Sekanina, Zdenek Vasícek, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel Oliveira, Fernando Fernandes, Stefano Di Carlo
2017	—	`conf`	Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. ISVLSI Muhammad Shafique, Rehan Hafiz, Muhammad Usama Javed, Sarmad Abbas, Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek
2017	A	`conf`	Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. ICCAD Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
2017	A	`conf`	EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. DATE Vojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina
2017	—	`conf`	Parallel optimization of transistor level circuits using cartesian genetic programming. GECCO (Companion) Vojtech Mrazek, Zdenek Vasícek
2017	A	`conf`	Towards low power approximate DCT architecture for HEVC standard. DATE Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2017	J	`jnl`	Trading between quality and non-functional properties of median filter in embedded systems. Genet. Program. Evolvable Mach. Zdenek Vasícek, Vojtech Mrazek
2016	—	`conf`	Automatic design of approximate circuits by means of multi-objective evolutionary algorithms. DTIS Radek Hrbacek, Vojtech Mrazek, Zdenek Vasícek
2016	—	`conf`	Automatic design of arbitrary-size approximate sorting networks with error guarantee. PATMOS Vojtech Mrazek, Zdenek Vasícek
2016	A	`conf`	Design of power-efficient approximate multipliers for approximate artificial neural networks. ICCAD Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy
2016	J	`jnl`	Evolutionary design of complex approximate combinational circuits. Genet. Program. Evolvable Mach. Zdenek Vasícek, Lukás Sekanina
2016	—	`conf`	Evolutionary functional approximation of circuits implemented into FPGAs. SSCI Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
2016	B	`conf`	Search-based synthesis of approximate circuits implemented into FPGAs. FPL Zdenek Vasícek, Lukás Sekanina
2015	C	`conf`	Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. EUC Vojtech Mrazek, Zdenek Vasícek
2015	B	`conf`	Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates. EuroGP Zdenek Vasícek
2015	B	`conf`	Circuit Approximation Using Single- and Multi-objective Cartesian GP. EuroGP Zdenek Vasícek, Lukás Sekanina
2015	J	`jnl`	Evolutionary Approach to Approximate Digital Circuits Design. IEEE Trans. Evol. Comput. Zdenek Vasícek, Lukás Sekanina
2015	—	`conf`	Evolutionary Approximation of Complex Digital Circuits. GECCO (Companion) Zdenek Vasícek, Lukás Sekanina
2015	—	`conf`	Evolutionary Approximation of Software for Embedded Systems: Median Function. GECCO (Companion) Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
2015	B	`conf`	Evolutionary Design of Transistor Level Digital Circuits Using Discrete Simulation. EuroGP Vojtech Mrazek, Zdenek Vasícek
2015	—	`ch.`	Functional Equivalence Checking for Evolution of Complex Digital Circuits. Evolvable Hardware Lukás Sekanina, Zdenek Vasícek
2014	—	`conf`	Acceleration of transistor-level evolution using Xilinx Zynq Platform. ICES Vojtech Mrazek, Zdenek Vasícek
2014	B	`conf`	Cartesian genetic programming as local optimizer of logic networks. IEEE Congress on Evolutionary Computation Lukás Sekanina, Ondrej Ptak, Zdenek Vasícek
2014	C	`conf`	Evolutionary design of approximate multipliers under different error metrics. DDECS Zdenek Vasícek, Lukás Sekanina
2014	—	`conf`	How to evolve complex combinational circuits from scratch? ICES Zdenek Vasícek, Lukás Sekanina
2014	B	`conf`	On Evolution of Multi-category Pattern Classifiers Suitable for Embedded Systems. EuroGP Zdenek Vasícek, Michal Bidlo
2014	—	`conf`	On Evolutionary Approximation of Logic Circuits. Computing with New Resources Lukás Sekanina, Zdenek Vasícek
2013	—	`conf`	Approximate circuit design by means of evolvable hardware. ICES Lukás Sekanina, Zdenek Vasícek
2013	B	`conf`	Evolution of cellular automata with conditionally matching rules. IEEE Congress on Evolutionary Computation Michal Bidlo, Zdenek Vasícek
2013	J	`jnl`	Evolution of efficient real-time non-linear image filters for FPGAs. Soft Comput. Zdenek Vasícek, Michal Bidlo, Lukás Sekanina
2013	—	`conf`	Functional-level development of image filters by means of cellular automata. ICES Michal Bidlo, Zdenek Vasícek
2013	J	`jnl`	Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit. Inf. Technol. Control. Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Václav Simek, Petr Hanácek
2012	A	`conf`	A SAT-based fitness function for evolutionary optimization of polymorphic circuits. DATE Lukás Sekanina, Zdenek Vasícek
2012	—	`—`	Acceleration Methods for Evolutionary Design of Digital Circuits. Zdenek Vasícek
2012	—	`conf`	Cellular Automaton as Sorting Network Generator Using Instruction-Based Development. ACRI Michal Bidlo, Zdenek Vasícek
2012	B	`conf`	Efficient Phenotype Evaluation in Cartesian Genetic Programming. EuroGP Zdenek Vasícek, Karel Slaný
2012	B	`conf`	Evolution of cellular automata using instruction-based approach. IEEE Congress on Evolutionary Computation Michal Bidlo, Zdenek Vasícek
2012	B	`conf`	On area minimization of complex combinational circuits using cartesian genetic programming. IEEE Congress on Evolutionary Computation Zdenek Vasícek, Lukás Sekanina
2012	B	`conf`	Two-step evolution of polymorphic circuits for image multi-filtering. IEEE Congress on Evolutionary Computation Lukás Sekanina, Vojtech Salajka, Zdenek Vasícek
2011	A	`conf`	A global postsynthesis optimization method for combinational circuits. DATE Zdenek Vasícek, Lukás Sekanina
2011	—	`ch.`	CGP Acceleration Using Field-Programmable Gate Arrays. Cartesian Genetic Programming Lukás Sekanina, Zdenek Vasícek
2011	—	`conf`	Evolutionary design of efficient and robust switching image filters. AHS Zdenek Vasícek, Michal Bidlo, Lukás Sekanina, Kyrre Glette
2011	B	`conf`	Evolutionary design of robust noise-specific image filters. IEEE Congress on Evolutionary Computation Zdenek Vasícek, Michal Bidlo
2011	J	`jnl`	Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genet. Program. Evolvable Mach. Zdenek Vasícek, Lukás Sekanina
2010	A	`conf`	A method for design of impulse bursts noise filters optimized for FPGA implementations. DATE Zdenek Vasícek, Lukás Sekanina, Michal Bidlo
2010	C	`conf`	On logic synthesis of conventionally hard to synthesize circuits using genetic programming. DDECS Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina
2010	—	`conf`	Sorting Network Development Using Cellular Automata. ICES Michal Bidlo, Zdenek Vasícek, Karel Slaný
2009	—	`conf`	Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits. AHS Michal Bidlo, Zdenek Vasícek
2009	A	`conf`	Development of combinational circuits using non-uniform cellular automata: initial results. GECCO Michal Bidlo, Zdenek Vasícek
2009	—	`conf`	Evolution of Impulse Bursts Noise Filters. AHS Zdenek Vasícek, Michal Bidlo, Lukás Sekanina, Jim Tørresen, Kyrre Glette, Marcus Furuholmen
2009	B	`conf`	Investigating gate-level evolutionary development of combinational multipliers using enhanced cellular automata-based model. IEEE Congress on Evolutionary Computation Michal Bidlo, Zdenek Vasícek
2009	—	`conf`	REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware. WEAH Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Roman Prokop, Lukás Fujcik
2008	—	`conf`	Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. AHS Zdenek Vasícek, Ladislav Capka, Lukás Sekanina
2008	—	`conf`	Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study. ICES Michal Bidlo, Zdenek Vasícek
2008	—	`conf`	Gate-Level Evolutionary Development Using Cellular Automata. AHS Michal Bidlo, Zdenek Vasícek
2008	B	`conf`	Hardware Accelerators for Cartesian Genetic Programming. EuroGP Zdenek Vasícek, Lukás Sekanina
2008	C	`conf`	Novel Hardware Implementation of Adaptive Median Filters. DDECS Zdenek Vasícek, Lukás Sekanina
2008	—	`conf`	On Evolutionary Synthesis of Linear Transforms in FPGA. ICES Zdenek Vasícek, Martin Zádník, Lukás Sekanina, Jirí Tobola
2007	B	`conf`	An area-efficient alternative to adaptive median filtering in FPGAs. FPL Zdenek Vasícek, Lukás Sekanina
2007	—	`conf`	Evaluation of a New Platform For Image Filter Evolution. AHS Zdenek Vasícek, Lukás Sekanina
2007	—	`conf`	Reducing the Area on a Chip Using a Bank of Evolved Filters. ICES Zdenek Vasícek, Lukás Sekanina
2006	—	`conf`	On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. EvoWorkshops Lukás Sekanina, Zdenek Vasícek