Zdenek Pohl

14 papers A 4B 6Journal 2Unranked 2
YearRankTypeTitle / Venue / Authors
2017 — conf
A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC^2.
SAFECOMP Workshops
Haris Isakovic, Radu Grosu, Denise Ratasich, Jiri Kadlec, Zdenek Pohl, Steve Kerrison, Kyriakos Georgiou, Kerstin Eder, Norbert Druml, Lillian Tadros, Flemming Christensen, Emilie Wheatley, Bastian Farkas, Rolf Meyer, Mladen Berekovic
2011 — conf
A Framework for Self-adaptive Collaborative Computing on Reconfigurable Platforms.
PARCO
Michiel W. van Tol, Zdenek Pohl, Milan Tichý
2011 B conf
Resource Management for the Heterogeneous Arrays of Hardware Accelerators.
FPL
Zdenek Pohl, Milan Tichý
2008 J jnl
Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA.
EURASIP J. Adv. Signal Process.
Zdenek Pohl, Milan Tichý, Jiri Kadlec
2008 J jnl
The European Logarithmic Microprocesor.
IEEE Trans. Computers
John N. Coleman, Christopher I. Softley, Jiri Kadlec, Rudolf Matousek, Milan Tichý, Zdenek Pohl, Antonin Hermanek, Nico F. Benschop
2007 B conf
RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor.
FPL
Zdenek Pohl, Milan Tichý
2005 B conf
Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration.
FPL
Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl
2005 A conf
Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only).
FPGA
Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl
2005 B conf
Performance Tuning of Iterative Algorithms in Signal Processing.
FPL
Zdenek Pohl, Premysl Sucha, Jiri Kadlec, Zdenek Hanzálek
2004 A conf
Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit.
IEEE Real-Time and Embedded Technology and Applications Symposium
Premysl Sucha, Zdenek Pohl, Zdenek Hanzálek
2003 B conf
FPGA Implementation of the Adpaptive Lattice Filter.
FPL
Antonin Hermanek, Zdenek Pohl, Jiri Kadlec
2003 A conf
Lattice adaptive filter implementation for FPGA.
FPGA
Zdenek Pohl, Rudolf Matousek, Jiri Kadlec, Milan Tichý, Miroslav Lícko
2003 A conf
Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based Rapid-FPGA-Prototyping.
IPDPS
Zdenek Pohl, Jan Schier, Miroslav Lícko, Antonin Hermanek, Milan Tichý, Rudolf Matousek, Jiri Kadlec
2002 B conf
Logarithmic Number System and Floating-Point Arithmetics on FPGA.
FPL
Rudolf Matousek, Milan Tichý, Zdenek Pohl, Jiri Kadlec, Christopher I. Softley, Nick Coleman