Zdenek Kotásek

95 papers B 1C 49Journal 10Unranked 33

Year	Rank	Type	Title / Venue / Authors
2021	C	`conf`	Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs. DSD Jakub Lojda, Richard Panek, Zdenek Kotásek
2021	—	`conf`	Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery. EWDTS Jakub Lojda, Richard Panek, Zdenek Kotásek
2021	C	`conf`	Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. DSD Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2021	—	`conf`	Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. LATS Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020	—	`conf`	Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. EWDTS Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020	C	`conf`	Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. DDECS Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Martin Krcma, Zdenek Kotásek
2020	—	`conf`	Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. LASCAS Jakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020	C	`conf`	Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. DSD Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020	—	`conf`	Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination. LASCAS Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek
2020	—	`conf`	Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. VLSI-DAT Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2019	—	`conf`	Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. LATS Karel Szurman, Zdenek Kotásek
2019	—	`conf`	Detecting hard synapses faults in artificial neural networks. LATS Martin Krcma, Zdenek Kotásek, Jakub Lojda
2019	—	`conf`	Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. LATS Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek
2019	C	`conf`	Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. DSD Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek
2019	—	`conf`	Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. LATS Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2019	C	`conf`	Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430. DDECS Karel Szurman, Zdenek Kotásek
2019	C	`conf`	Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. DSD Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek
2018	—	`conf`	A Processor Optimization Framework for a Selected Application. EWDTS Jalab Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek
2018	—	`conf`	An Experimental Evaluation of Fault-Tolerant FPGA-Based Robot Controller. EWDTS Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek
2018	C	`conf`	Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller. DSD Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotásek
2018	C	`conf`	FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. DSD Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek
2018	—	`conf`	Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. EWDTS Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2018	—	`conf`	Input and Output Generation for the Verification of ALU: A Use Case. EWDTS Ondrej Cekan, Richard Panek, Zdenek Kotásek
2018	—	`conf`	Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. EWDTS Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2018	C	`conf`	Program Generation Through a Probabilistic Constrained Grammar. DSD Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek
2017	C	`conf`	A Probabilistic Context-Free Grammar Based Random Test Program Generation. DSD Ondrej Cekan, Zdenek Kotásek
2017	B	`conf`	Comparison of FPNNs models approximation capabilities and FPGA resources utilization. ICCP Martin Krcma, Zdenek Kotásek, Jakub Lojda
2017	—	`conf`	Data types and operations modifications: A practical approach to fault tolerance in HLS. EWDTS Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek, Martin Krcma
2017	J	`jnl`	Functional verification based platform for evaluating fault tolerance properties. Microprocess. Microsystems Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Marcela Zachariásová, Martin Krcma, Zdenek Kotásek
2017	—	`conf`	Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluation. EWDTS Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2017	C	`conf`	Reliability Analysis and Improvement of FPGA-Based Robot Controller. DSD Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek
2017	—	`conf`	Triple modular redundancy used in field programmable neural networks. EWDTS Martin Krcma, Zdenek Kotásek, Jakub Lojda
2016	—	`conf`	Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs. FPT Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek
2016	—	`conf`	HLS-based fault tolerance approach for SRAM-based FPGAs. FPT Jakub Lojda, Jakub Podivinsky, Martin Krcma, Zdenek Kotásek
2016	—	`conf`	Implementation of fault tolerant techniques into FPNNs. FPT Martin Krcma, Zdenek Kotásek, Jakub Lojda
2016	—	`conf`	Random stimuli generation based on a stochastic context-free grammar. FPT Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek
2016	C	`conf`	Regression Test Suites Optimization for Application-specific Instruction-Set Processors and Their Use for Dependability Analysis. DSD Marcela Zachariásová, Michaela Kekelyova-Beleova, Zdenek Kotásek
2016	C	`conf`	Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems. DSD Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek
2015	C	`conf`	Application of Evolutionary Algorithms for Regression Suites Optimization. DDECS Michaela Beleova, Zdenek Kotásek, Marcela Simková, Toma Hruka
2015	C	`conf`	Automation and Optimization of Coverage-driven Verification. DSD Marcela Simková, Zdenek Kotásek
2015	C	`conf`	FPGA Prototyping and Accelerated Verification of ASIPs. DDECS Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek
2015	—	`conf`	Fault tolerant Field Programmable Neural Networks. NORCAS Martin Krcma, Zdenek Kotásek, Jan Kastil
2015	C	`conf`	Mapping Trained Neural Networks to FPNNs. DDECS Martin Krcma, Jan Kastil, Zdenek Kotásek
2015	C	`conf`	Software Fault Tolerance: The Evaluation by Functional Verification. DSD Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek
2015	J	`jnl`	The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applications. Microprocess. Microsystems Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek
2014	C	`conf`	Automatic Construction of On-line Checking Circuits Based on Finite Automata. DSD Lucie Matuova, Jan Kastil, Zdenek Kotásek
2014	C	`conf`	Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA. DDECS Lukas Miculka, Zdenek Kotásek
2014	C	`conf`	State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. DSD Karel Szurman, Lukas Miculka, Zdenek Kotásek
2014	C	`conf`	The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications. DSD Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek
2013	C	`conf`	Analysis and comparison of functional verification and ATPG for testing design reliability. DDECS Marcela Simková, Zdenek Kotásek, Cristiana Bolchini
2013	—	`conf`	Automated Functional Verification of Application Specific Instruction-set Processors. IESS Marcela Simková, Zdenek Prikryl, Zdenek Kotásek, Tomas Hruska
2013	C	`conf`	Fault tolerant CAN bus control system implemented into FPGA. DDECS Karel Szurman, Jan Kastil, Martin Straka, Zdenek Kotásek
2013	J	`jnl`	Fault tolerant system design and SEU injection based testing. Microprocess. Microsystems Martin Straka, Jan Kastil, Zdenek Kotásek, Lukas Miculka
2013	C	`conf`	Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant Area. DSD Lukas Miculka, Martin Straka, Zdenek Kotásek
2012	C	`conf`	Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. DSD Jan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotásek
2012	—	`ed.`	Mathematical and Engineering Methods in Computer Science - 7th International Doctoral Workshop, MEMICS 2011, Lednice, Czech Republic, October 14-16, 2011, Revised Selected Papers MEMICS Zdenek Kotásek, Jan Bouda, Ivana Cerná, Lukás Sekanina, Tomás Vojnar, David Antos
2012	C	`conf`	Test platform for fault tolerant systems design properties verification. DDECS Martin Straka, Lukas Miculka, Jan Kastil, Zdenek Kotásek
2012	J	`jnl`	pecial CAI Section Devoted to MEMICS '11: Preface. Comput. Informatics Zdenek Kotásek, Lukás Sekanina, Tomás Vojnar, Jan Bouda, Ivana Cerná
2011	C	`conf`	Advanced fault tolerant bus for multicore system implemented in FPGA. DDECS Martin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek
2011	C	`conf`	Decreasing test time by scan chain reorganization. DDECS Pavel Bartos, Zdenek Kotásek, Jan Dohnal
2011	C	`conf`	SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems. DSD Martin Straka, Jan Kastil, Zdenek Kotásek
2010	C	`ed.`	13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010 DDECS Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann
2010	C	`conf`	Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration. DSD Martin Straka, Jan Kastil, Zdenek Kotásek
2010	C	`conf`	Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs. DDECS Martin Straka, Jan Kastil, Zdenek Kotásek
2010	C	`conf`	Reduction of power dissipation through parallel optimization of test vector and scan register sequences. DDECS Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel
2010	C	`conf`	The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. DSD Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel
2010	—	`conf`	The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. ICES Jaroslav Skarvada, Zdenek Kotásek, Josef Strnadel
2009	C	`conf`	High Availability Fault Tolerant Architectures Implemented into FPGAs. DSD Martin Straka, Zdenek Kotásek
2009	—	`ed.`	Proceedings of the International Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, MEMICS 2008, Znojmo, Czech Republic, November 14-16, 2008 MEMICS Milan Ceska, Zdenek Kotásek, Mojmír Kretínský, Ludek Matyska, Tomás Vojnar
2008	C	`conf`	Digital Systems Architectures Based on On-line Checkers. DSD Martin Straka, Zdenek Kotásek, Jan Winter
2008	J	`jnl`	Evolution of synthetic RTL benchmark circuits with predefined testability. ACM Trans. Design Autom. Electr. Syst. Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek
2008	J	`jnl`	Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits. Comput. Informatics Josef Strnadel, Tomas Pecenka, Zdenek Kotásek
2008	J	`jnl`	Polymorphic Gates in Design and Test of Digital Circuits. Int. J. Unconv. Comput. Lukás Sekanina, Lukás Starecek, Zdenek Kotásek, Zbysek Gajda
2008	C	`conf`	Power Conscious RTL Test Scheduling. DSD Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman
2008	—	`conf`	Preface. MEMICS Milan Ceska, Zdenek Kotásek, Mojmír Kretínský, Ludek Matyska, Tomás Vojnar
2008	C	`conf`	Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. DDECS Lukás Starecek, Lukás Sekanina, Zdenek Kotásek
2008	J	`jnl`	Testability analysis based on the identification of testable blocks with predefined properties. Microprocess. Microsystems Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman
2007	—	`conf`	Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. DFT Martin Straka, Jiri Tobola, Zdenek Kotásek
2007	C	`conf`	Online Protocol Testing for FPGA Based Fault Tolerant Systems. DSD Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka
2007	C	`conf`	Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. DSD Jaroslav Skarvada, Tomas Herrman, Zdenek Kotásek
2006	—	`conf`	Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. AHS Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek
2006	C	`conf`	FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. DDECS Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina
2006	C	`conf`	Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. DDECS Lukás Sekanina, Lukás Starecek, Zdenek Kotásek
2006	C	`ed.`	Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006 DDECS Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek
2006	—	`conf`	SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. ECBS Josef Strnadel, Zdenek Kotásek
2006	C	`conf`	Testability Estimation Based on Controllability and Observability Parameters. DSD Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina
2005	—	`conf`	Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Evolvable Hardware Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel
2005	C	`conf`	Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. DSD Josef Strnadel, Zdenek Kotásek
2004	—	`conf`	The Identification of registers in RTL Structures for the Test Application. ISoLA (Preliminary proceedings) Daniel Mika, Josef Strnadel, Zdenek Kotásek
2003	C	`conf`	Test scheduling for embedded systems. DSD Zdenek Kotásek, Daniel Mika, Josef Strnadel
2002	C	`conf`	Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. DSD Josef Strnadel, Zdenek Kotásek
2000	—	`conf`	Formal Approach to the RTL Testability Analysis. LATW Zdenek Kotásek, Richard Ruzicka, Jan Hlavicka
1997	J	`jnl`	RT Level Test Scheduling. Comput. Artif. Intell. Jan Blatný, Zdenek Kotásek, Jan Hlavicka
1997	—	`conf`	RT level testability analysis to reduce test application time. EUROMICRO Zdenek Kotásek, F. Zboril
1995	J	`jnl`	I-Path Analysis. Comput. Artif. Intell. Jan Blatný, Zdenek Kotásek