Zarrin Tasnim Sworna

14 papers A 1B 1C 1Misc 1Journal 9Unranked 1
YearRankTypeTitle / Venue / Authors
2024 J jnl
The ethical implications of Chatbot developments for conservation expertise.
AI Ethics
Zarrin Tasnim Sworna, Danilo Urzedo, Andrew J. Hoskins, Catherine J. Robinson
2023 J jnl
APIRO: A Framework for Automated Security Tools API Recommendation.
ACM Trans. Softw. Eng. Methodol.
Zarrin Tasnim Sworna, Chadni Islam, Muhammad Ali Babar
2023 A conf
IRP2API: Automated Mapping of Cyber Security Incident Response Plan to Security Tools' APIs.
SANER
Zarrin Tasnim Sworna, Muhammad Ali Babar, Anjitha Sreekumar
2023 J jnl
NLP methods in host-based intrusion detection systems: A systematic review and future directions.
J. Netw. Comput. Appl.
Zarrin Tasnim Sworna, Zahra Mousavi, Muhammad Ali Babar
2023 B conf
Security Tools' API Recommendation Using Machine Learning.
ENASE
Zarrin Tasnim Sworna, Anjitha Sreekumar, Chadni Islam, Muhammad Ali Babar
2022 J jnl
"I think this is the most disruptive technology": Exploring Sentiments of ChatGPT Early Adopters using Twitter Data.
CoRR
Mubin Ul Haque, Isuru Dharmadasa, Zarrin Tasnim Sworna, Roshan Namal Rajapakse, Hussain Ahmad
2022 J jnl
A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design.
CoRR
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal
2022 J jnl
APIRO: A Framework for Automated Security Tools API Recommendation.
CoRR
Zarrin Tasnim Sworna, Chadni Islam, Muhammad Ali Babar
2022 J jnl
NLP Methods in Host-based Intrusion Detection Systems: A Systematic Review and Future Directions.
CoRR
Zarrin Tasnim Sworna, Zahra Mousavi, Muhammad Ali Babar
2018 J jnl
A Fast FPGA-Based BCD Adder.
Circuits Syst. Signal Process.
Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu, Ashis Kumer Biswas
2017 — conf
An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem.
ISVLSI
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas
2016 C conf
A LUT-based matrix multiplication using neural networks.
ISCAS
Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu
2016 Misc conf
An Improved Design of a Reversible Fault Tolerant LUT-based FPGA.
VLSID
Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu
2016 J jnl
Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array.
IET Circuits Devices Syst.
Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md. Hasan Babu, Ashis Kumer Biswas