Zainalabedin Navabi

216 papers A* 2A 11B 13C 31Misc 10Journal 43Unranked 104

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Quasi Fat Tree-based Formation of Micro-Programmable Processing Elements for Machine Learning Applications. ISVLSI Sepideh Kheirollahi, Sinatra Babele Khanshan, Zainalabedin Navabi
2025	—	`conf`	An Event-Based Gate-Level Framework for Power Side-Channel Leakage Assessment. ISVLSI Katayoon Basharkhah, Zahra Hojati, Zainalabedin Navabi
2025	B	`conf`	An Integrated Framework for Aging Analysis Based on an Age-Aware Cell Library. ETS Amirmahdi Joudi, Negin Safari, Fatemeh MohammadZadeh, Katayoon Basharkhah, Fatemeh Sheikhshoaei, Zainalabedin Navabi
2025	C	`conf`	Domain-Specific Design Abstraction with Emphasis on Neural Networks. DDECS Maryam Rajabalipanah, Zahra Hojati, Zahra Jahanpeima, Zainalabedin Navabi
2025	J	`jnl`	SCiMA: A Systolic CiM-Based Accelerator With a New Weight Mapping for CNNs - A Virtual Framework Approach. IEEE Access Rezgar Sadeghi, Zainalabedin Navabi
2024	—	`conf`	A Hierarchy of Machine Learning Processing Elements with Joint Micro Programmable Computation and Indexing. EWDTS Sepideh Kheirollahi, Sinatra Babele Khanshan, Zainalabedin Navabi
2024	—	`conf`	AZMA: A Zynq-Based Monitoring and Fault Injection Framework for Processor Assessment. EWDTS Zahra Mahdavi, Rezgar Sadeghi, Ali Shayanpour, Amirhosein Yazdanpanah, Zainalabedin Navabi
2024	J	`jnl`	An Efficient RTL Design for a Wearable Brain-Computer Interface. IET Comput. Digit. Tech. Tahereh Vasei, Mohammad Ali Saber, Alireza Nahvy, Zainalabedin Navabi
2024	J	`jnl`	Analysis and Enhancement of Resilience for LSTM Accelerators Using Residue-Based CEDs. IEEE Access Nooshin Nosrati, Zainalabedin Navabi
2024	—	`conf`	Configurable DRAM Access for Neural Network Accelerators: A SystemC Virtual Platform Approach. EWDTS Tina Hashemi, Rezgar Sadeghi, Maryam Rajabalipanah, Zahra Hojati, Zainalabedin Navabi
2024	—	`conf`	Event-Based Power Analysis Integrated with Timing Characterization and Logic Simulation. ISVLSI Katayoon Basharkhah, Zainalabedin Navabi
2024	—	`conf`	LBIST Configuration and Golden Signature Extraction of Black Box IP Cores. EWDTS Fatemeh MohammadZadeh, Zeynab Sanati Najar, Zainalabedin Navabi
2024	J	`jnl`	Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators. IEEE Trans. Very Large Scale Integr. Syst. Alireza Nahvy, Zainalabedin Navabi
2024	—	`conf`	Real-Time Automotive Accident Detection Using Unsupervised Machine Learning. EWDTS Reza Baharvand, Mahsa Jamshidi, Mozhgan Rezaie Manavand, Rezgar Sadeghi, Zainalabedin Navabi
2024	—	`conf`	Sharing AES Engine for RISC-V Custom Instructions Performing Encryption and Decryption. EWDTS Zahra Hojati, Zahra Jahanpeima, Maryam Rajabalipanah, Hossein Ta'ati, Atefe Rabiei, Zainalabedin Navabi
2023	C	`conf`	A Low-Cost Combinational Approximate Multiplier. DDECS Zahra Hojati, Zainalabedin Navabi
2023	C	`conf`	A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators. DDECS Nooshin Nosrati, Zainalabedin Navabi
2023	—	`conf`	HIRMA: High-Performance Implementation for RISC-V Microcontroller Applications. EWDTS Negin Safari, Amirmahdi Joudi, Maryam Rajabalipanah, Zahra Jahanpeima, Hasan Sadeghzadeh, Zainalabedin Navabi
2023	B	`conf`	Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction. ETS Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Zainalabedin Navabi
2023	—	`conf`	Multi-Level Fault Injection Methodology Using UVM-SystemC. EWDTS Ebrahim Nouri, Nooshin Nosrati, Hanieh Totonchi Asl, Mozhgan Rezaie Manavand, Zainalabedin Navabi
2022	—	`conf`	A Secure Canary-Based Hardware Approach Against ROP. ITASEC Mahboobe Sadeghipour Roodsari, Ebrahim Nouri, Fatemeh Sheikhshoaei, Paolo Prinetto, Zainalabedin Navabi
2022	B	`conf`	Concurrent Error Detection for LSTM Accelerators. ETS Nooshin Nosrati, Seyedeh Maryam Ghasemi, Mahboobe Sadeghipour Roodsari, Zainalabedin Navabi
2022	C	`conf`	MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors. IOLTS Nooshin Nosrati, Maksim Jenihhin, Zainalabedin Navabi
2022	J	`jnl`	Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity. CoRR Fatemeh Sheikh Shoaei, Alireza Nahvy, Zainalabedin Navabi
2021	—	`conf`	AFTAB: A RISC-V Implementation with Configurable Gateways for Security. EWDTS Maryam Rajabalipanah, Mahboobe Sadeghipour Roodsari, Zahra Jahanpeima, Gianluca Roascio, Paolo Prinetto, Zainalabedin Navabi
2021	C	`conf`	Integrating an Interconnect BIST with Crosstalk Avoidance Hardware. IOLTS Mahsa Akhsham, Zainalabedin Navabi
2021	B	`conf`	Online Testing of a Row-Stationary Convolution Accelerator. ETS Mohammad Rasoul Roshanshah, Katayoon Basharkhah, Zainalabedin Navabi
2021	—	`conf`	Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester. DTIS Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi
2021	—	`conf`	n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator. ISVLSI Mahboobe Sadeghipour Roodsari, Hanieh Totonchi Asl, Zainalabedin Navabi
2020	B	`conf`	Built-In Predictors for Dynamic Crosstalk Avoidance. ETS Rezgar Sadeghi, Zainalabedin Navabi
2020	C	`conf`	DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation. DDECS Mahboobe Sadeghipour Roodsari, Mohamad Ali Saber, Zainalabedin Navabi
2020	Misc	`conf`	ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links. VTS Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi
2020	J	`jnl`	LUT Input Reordering to Reduce Aging Impact on FPGA LUTs. IEEE Trans. Computers Mohammad Ebrahimi, Rezgar Sadeghi, Zainalabedin Navabi
2020	C	`conf`	Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations. DDECS Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Zainalabedin Navabi
2020	—	`conf`	Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator. DFT Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi
2020	J	`jnl`	Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohammad Ebrahimi, Zainalabedin Navabi
2020	J	`jnl`	Self-Adjusting Monitor for Measuring Aging Rate and Advancement. IEEE Trans. Emerg. Top. Comput. Somayeh Sadeghi Kohan, Mehdi Kamal, Zainalabedin Navabi
2019	—	`conf`	An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. EWDTS Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi
2019	—	`conf`	An ESL Environment for Modeling Electrical Interconnect Faults. ISVLSI Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi
2019	B	`conf`	Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. ETS Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi
2019	—	`conf`	From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization. EWDTS Samira Ahmadi Farsani, Katayoon Basharkhah, Amin Mohaghegh, Zainalabedin Navabi
2019	—	`conf`	Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment. EWDTS Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi
2019	—	`conf`	SCOAP-based Directed Random Test Generation for Combinational Circuits. EWDTS Seyyede Maryam Ghasemy, Maryam Rajabalipanah, Saeideh Sarmadi, Zainalabedin Navabi
2019	B	`conf`	Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme. ETS Mahsa Akhsham, Atefesadat Seyedolhosseini, Zainalabedin Navabi
2018	J	`jnl`	Automatic Correction of Dynamic Power Management Architecture in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. Reza Sharafinejad, Bijan Alizadeh, Zainalabedin Navabi
2018	C	`conf`	Near-Optimal Node Selection Procedure for Aging Monitor Placement. IOLTS Somayeh Sadeghi Kohan, Arash Vafaei, Zainalabedin Navabi
2018	—	`conf`	Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. ACM Great Lakes Symposium on VLSI Ramin Rezaeizadeh Rookerd, Somayeh Sadeghi Kohan, Zainalabedin Navabi
2018	J	`jnl`	Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
2017	—	`conf`	A novel SAT-based ATPG approach for transition delay faults. HLDVT Farzaneh Zokaee, Hossein Sabaghian Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi
2017	J	`jnl`	An Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture. CoRR Elaheh Sadredini, Reza Rahimi, Paniz Foroutan, Mahmood Fathy, Zainalabedin Navabi
2017	J	`jnl`	BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding. CoRR Elaheh Sadredini, Mohammadreza Najafi, Mahmood Fathy, Zainalabedin Navabi
2017	J	`jnl`	Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
2017	B	`conf`	Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems. ETS Rasool Sharifi, Zainalabedin Navabi
2017	—	`conf`	Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach. ISVLSI Hossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi
2017	J	`jnl`	SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs. IEEE Trans. Computers Zana Ghaderi, Mohammad Ebrahimi, Zainalabedin Navabi, Eli Bozorgzadeh, Nader Bagherzadeh
2017	J	`jnl`	Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint. CoRR Elaheh Sadredini, Mohammad Hashem Haghbayan, Mahmood Fathy, Zainalabedin Navabi
2017	A	`conf`	TruncApp: A truncation-based approximate divider for energy efficient DSP applications. DATE Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Zainalabedin Navabi
2016	—	`conf`	An improved scheme for pre-computed patterns in core-based SoC architecture. EWDTS Elaheh Sadredini, Reza Rahimi, Paniz Foroutan, Mahmood Fathy, Zainalabedin Navabi
2016	—	`conf`	ESL design with RTL-verified predesigned abstract communication channels. EWDTS Hamed Najafi Haghi, Mikhail M. Chupilko, Alexander S. Kamkin, Zainalabedin Navabi
2016	C	`conf`	Optimistic clock adjustment for preventing Better-than-worst-case violations. VLSI-SoC Seyedeh Hanieh Hashemi, Reza Namazian, Zainalabedin Navabi
2016	—	`conf`	Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping. ACM Great Lakes Symposium on VLSI Morteza Soltani, Mohammad Ebrahimi, Zainalabedin Navabi
2016	J	`jnl`	Self-Healing Many-Core Architecture: Analysis and Evaluation. VLSI Design Arezoo Kamran, Zainalabedin Navabi
2016	J	`jnl`	Stochastic testing of processing cores in a many-core architecture. Integr. Arezoo Kamran, Zainalabedin Navabi
2016	—	`conf`	Universal mitigation of NBTI-induced aging by design randomization. EWDTS Maksim Jenihhin, Alexander Kamkin, Zainalabedin Navabi, Somayeh Sadeghi Kohan
2015	J	`jnl`	A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies. Integr. Mohammad Ansari, Hassan Afzali-Kusha, Behzad Ebrahimi, Zainalabedin Navabi, Ali Afzali-Kusha, Massoud Pedram
2015	—	`conf`	Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model. MCSoC Elmira Karimi, Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mahmoud Tabandeh, Pasi Liljeberg, Zainalabedin Navabi
2015	—	`conf`	Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. DTIS Somayeh Sadeghi Kohan, Arezoo Kamran, Farnaz Forooghifar, Zainalabedin Navabi
2015	—	`conf`	Application-specific power-aware mapping for reconfigurable NoC architectures. DTIS Mehran Goli, Amin Ghasemazar, Zainalabedin Navabi
2015	J	`jnl`	Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. IEEE Trans. Computers Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
2015	—	`conf`	HDLs evolve as they affect design methodology for a higher abstraction and a better integration. DTIS Zainalabedin Navabi
2015	—	`conf`	Low power scheduling in high-level synthesis using dual-Vth library. ISQED Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi
2015	—	`conf`	Multi-valued logic test access mechanism for test time and power reduction. DTIS Amirreza Nekooei, Zainalabedin Navabi
2015	A	`conf`	Power-aware online testing of manycore systems in the dark silicon era. DATE Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Zainalabedin Navabi, Hannu Tenhunen
2015	Misc	`conf`	Signature oriented model pruning to facilitate multi-threaded processors debugging. VTS Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
2015	J	`jnl`	System-level assertions: approach for electronic system-level verification. IET Comput. Digit. Tech. Hasan Sohofi, Zainalabedin Navabi
2014	—	`conf`	A heuristic path selection method for small delay defects test. DFT Paniz Foroutan, Mehdi Kamal, Zainalabedin Navabi
2014	B	`conf`	An off-line MDSI interconnect BIST incorporated in BS 1149.1. ETS Marzieh Mohammadi, Somayeh Sadeghi Kohan, Nasser Masoumi, Zainalabedin Navabi
2014	—	`conf`	Assertion-based verification for system-level designs. ISQED Hasan Sohofi, Zainalabedin Navabi
2014	B	`conf`	Automatic correction of certain design errors using mutation technique. ETS Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi
2014	—	`conf`	Back-annotation of gate-level power properties into system level descriptions. NEWCAS Najmeh Farajipour Ghohroud, Zainalabedin Navabi
2014	Misc	`conf`	Configurable Systolic Matrix Multiplication. VLSID Parastoo Kamranfar, Ali Shahabi, Ghazaleh Vazhbakht, Zainalabedin Navabi
2014	—	`conf`	Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits. ISVLSI Farimah Farahmandi, Bijan Alizadeh, Zainalabedin Navabi
2014	B	`conf`	Homogeneous many-core processor system test distribution and execution mechanism. ETS Arezoo Kamran, Zainalabedin Navabi
2014	B	`conf`	Improving polynomial datapath debugging with HEDs. ETS Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
2014	—	`conf`	Preemptive multi-bit IJTAG testing with reconfigurable infrastructure. DFT Shahrzad Keshavarz, Amirreza Nekooei, Zainalabedin Navabi
2014	—	`conf`	RTL datapath optimization using system-level transformations. ISQED Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
2013	J	`jnl`	A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits. IEEE Des. Test Mohammad Mirzaei, Mahmoud Tabandeh, Bijan Alizadeh, Zainalabedin Navabi
2013	—	`conf`	A new structure for interconnect offline testing. EWDTS Somayeh Sadeghi Kohan, Shahrzad Keshavarz, Farzaneh Zokaee, Farimah Farahmandi, Zainalabedin Navabi
2013	—	`conf`	A probabilistic approach for counterexample generation to aid design debugging. EWDTS Payman Behnam, Hossein Sabaghian Bidgoli, Bijan Alizadeh, Kamyar Mohajerani, Zainalabedin Navabi
2013	—	`conf`	Extracting complete set of equations to analyze VHDL-AMS descriptions. EWDTS Arezoo Kamran, Vahid Janfaza, Zainalabedin Navabi
2013	C	`conf`	Online periodic test mechanism for homogeneous many-core processors. VLSI-SoC Arezoo Kamran, Zainalabedin Navabi
2012	—	`conf`	A Probabilistic and Constraint Based Approach for Low Power Test Generation. Asian Test Symposium Hossein Sabaghian Bidgoli, Majid Namaki-Shoushtari, Zainalabedin Navabi
2012	—	`conf`	A novel graceful degradable routing algorithm for 3D on-chip networks. INA-OCMC@HiPEAC Reza Nakhjavani, Ali Shahabi, Saeed Safari, Zainalabedin Navabi
2012	A	`conf`	BS 1149.1 extensions for an online interconnect fault detection and recovery. ITC Somayeh Sadeghi Kohan, Majid Namaki-Shoushtari, Fatemeh Javaheri, Zainalabedin Navabi
2012	C	`conf`	Effective RT-level software-based self-testing of embedded processor cores. DDECS Parisa Kabiri, Zainalabedin Navabi
2012	C	`conf`	Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2 MEMOCODE Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita
2012	C	`conf`	Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST. DDECS M. H. Haghbayan, Saeed Safari, Zainalabedin Navabi
2012	C	`conf`	Soft Error Analysis on Communication Channels in On-Chip Communication Networks. DSD Mohammadreza Najafi, Saeed Safari, Zainalabedin Navabi
2011	—	`conf`	Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing. Asian Test Symposium Nastaran Nemati, Zainalabedin Navabi
2011	—	`conf`	Configurable architecture for memory BIST. EWDTS Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi
2011	—	`conf`	Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware. Asian Test Symposium Fatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi
2011	—	`conf`	Online Test Macro Scheduling and Assignment in MPSoC Design. Asian Test Symposium Behnam Khodabandeloo, Seyyed Alireza Hoseini, Sajjad Taheri, Mohammad Hashem Haghbayan, Mahmood Reza Babaei, Zainalabedin Navabi
2010	—	`conf`	A TLM2.0 assertion library with centralized monitoring approach. EWDTS Amirali Ghofrani, Sheis Abolma'ali, Zahra Najafi Haghi, Zainalabedin Navabi
2010	—	`conf`	A mixed HDL/PLI test package. EWDTS Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi
2010	C	`conf`	A partitioning approach to improve reconfigurable neuron-inspired online BIST. IOLTS Ali Shahabi, S. Behdad Hosseini, Hasan Sohofi, Zainalabedin Navabi
2010	B	`conf`	A reconfigurable online BIST for combinational hardware using digital neural networks. ETS S. Behdad Hosseini, Ali Shahabi, Hasan Sohofi, Zainalabedin Navabi
2010	—	`conf`	Architecture design and technical methodology for bus testing. EWDTS M. H. Haghbayan, Zainalabedin Navabi
2010	—	`conf`	Assertion based verification in TLM. EWDTS Amirali Ghofrani, Fatemeh Javaheri, Zainalabedin Navabi
2010	—	`conf`	Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization. SoC Amirali Ghofrani, Fatemeh Javaheri, Saeed Safari, Zainalabedin Navabi
2010	—	`conf`	Code optimization for enhancing SystemC simulation time. EWDTS Homa Alemzadeh, Soheil Aminzadeh, Reihaneh Saberi, Zainalabedin Navabi
2010	J	`jnl`	EDXY - A low cost congestion-aware routing algorithm for network-on-chips. J. Syst. Archit. Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi
2010	—	`conf`	ESL design methodology for architecture exploration. EWDTS Fatemeh Javaheri, Zainalabedin Navabi
2010	—	`conf`	Facilitating testability of TLM FIFO: SystemC implementations. EWDTS Homa Alemzadeh, Marco Cimei, Paolo Prinetto, Zainalabedin Navabi
2010	—	`conf`	Generating test patterns for sequential circuits using random patterns by PLI functions. EWDTS Mohammad Hashem Haghbayan, Alireza Yazdanpanah, Sara Karamati, Ramyar Saeedi, Zainalabedin Navabi
2010	—	`conf`	Low cost error tolerant motion estimation for H.264/AVC standard. EWDTS Mohammad Hossein Sargolzaei, Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Zainalabedin Navabi
2010	—	`conf`	Merit based directed random test generation (MDRTG) scheme for combinational circuits. EWDTS Arezoo Kamran, Mohammad Saeed Jahangiry, Zainalabedin Navabi
2010	—	`conf`	Near optimal machine learning based random test generation. EWDTS Niki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi
2010	J	`jnl`	Real-time embedded emotional controller. Neural Comput. Appl. Mohammad Reza Jamali, Masood Deh-Yadegari, Arash Arami, Caro Lucas, Zainalabedin Navabi
2010	—	`conf`	Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment. Asian Test Symposium M. H. Haghbayan, Sara Karamati, Fatemeh Javaheri, Zainalabedin Navabi
2010	A	`conf`	Using context based methods for test data compression. ITC Sara Karamati, Zainalabedin Navabi
2010	—	`conf`	Virtual tester development using HDL/PLI. EWDTS Arezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi
2009	J	`jnl`	Emotion on FPGA: Model driven approach. Expert Syst. Appl. Mohammad Reza Jamali, Arash Arami, Masood Deh-Yadegari, Caro Lucas, Zainalabedin Navabi
2009	—	`conf`	Optimizing Parametric BIST Using Bio-inspired Computing Algorithms. DFT Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi
2009	J	`jnl`	Sign Bit Reduction Encoding For Low Power Applications. J. Signal Process. Syst. Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
2008	A	`conf`	"Plug & Test" at System Level via Testable TLM Primitives. ITC Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi
2008	C	`conf`	A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing. IOLTS Naghmeh Karimi, Soheil Aminzadeh, Saeed Safari, Zainalabedin Navabi
2008	J	`jnl`	A Selective Trigger Scan Architecture for VLSI Testing. IEEE Trans. Computers Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi
2008	—	`conf`	An IEEE 1500 compatible wrapper architecture for testing cores at transaction level. EWDTS Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi
2008	Misc	`conf`	An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations. VLSI Design Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi
2008	—	`conf`	An advanced method for synthesizing TLM2-based interfaces. EWDTS Nadereh Hatami, Zainalabedin Navabi
2008	—	`conf`	Automating Hardware/Software partitioning using dependency Graph. EWDTS Somayeh Malekshahi, Mahshid Sedghi, Zainalabedin Navabi
2008	A	`conf`	BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs. DATE Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, Zainalabedin Navabi
2008	Misc	`conf`	Enhanced TED: A New Data Structure for RTL Verification. VLSI Design Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi
2008	—	`conf`	Functional testing approaches for "BIFST-able" tlm_fifo. HLDVT Homa Alemzadeh, Zainalabedin Navabi, Stefano Di Carlo, Alberto Scionti, Paolo Prinetto
2008	A	`conf`	NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure. ITC Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Zainalabedin Navabi
2008	J	`jnl`	Online Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch Faults. J. Univers. Comput. Sci. Naghmeh Karimi, Armin Alaghi, Mahshid Sedghi, Zainalabedin Navabi
2008	C	`conf`	Reliability in Application Specific Mesh-Based NoC Architectures. IOLTS Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi
2008	—	`conf`	Reliable NoC architecture utilizing a robust rerouting algorithm. EWDTS Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Mahmood Fathy, Zainalabedin Navabi
2008	Misc	`conf`	Stall Power Reduction in Pipelined Architecture Processors. VLSI Design Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi
2008	—	`conf`	System level hardware design and simulation with SystemAda. EWDTS Negin Mahani, Parnian Mokri, Zainalabedin Navabi
2008	—	`conf`	Utilizing HDL simulation engines for accelerating design and test processes. EWDTS Najmeh Farajipour, S. Behdad Hosseini, Zainalabedin Navabi
2007	C	`conf`	A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library. FDL Parisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi
2007	C	`conf`	A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. DDECS Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
2007	C	`conf`	A New Approach for Design and Verification of Transaction Level Models. ISCAS Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi
2007	Misc	`conf`	A UML Based System Level Failure Rate Assessment Technique for SoC Designs. VTS Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi
2007	C	`conf`	APDL: A Processor Description Language For Design Space Exploration of Embedded Processors. FDL Nima Honarmand, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi
2007	C	`conf`	An Analytical Model for Reliability Evaluation of NoC Architectures. IOLTS Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi
2007	—	`conf`	An HDL-Based Platform for High Level NoC Switch Testing. ATS Mahshid Sedghi, Armin Alaghi, Elnaz Koopahi, Zainalabedin Navabi
2007	C	`conf`	Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IOLTS Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale
2007	J	`jnl`	Degradable mesh-based on-chip networks using programmable routing tables. IEICE Electron. Express Ali Shahabi, Nima Honarmand, Hasan Sohofi, Zainalabedin Navabi
2007	Misc	`conf`	High Level Synthesis of Degradable ASICs Using Virtual Binding. VTS Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi
2007	J	`jnl`	Low overhead DFT using CDFG by modifying controller. IET Comput. Digit. Tech. Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi
2007	J	`jnl`	Low test application time resource binding for behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi
2007	C	`conf`	On-Chip Verification of NoCs Using Assertion Processors. DSD Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
2007	—	`conf`	Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode. DFT Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi
2007	—	`conf`	Optimized Assignment Coverage Computation in Formal Verification of Digital Systems. ATS Majid Nabi, Hamid Shojaei, Siamak Mohammadi, Zainalabedin Navabi
2007	C	`conf`	Programmable Routing Tables for Degradable Torus-Based Networks on Chips. ISCAS Ali Shahabi, Nima Honarmand, Zainalabedin Navabi
2007	—	`conf`	RT level reliability enhancement by constructing dynamic TMRS. ACM Great Lakes Symposium on VLSI Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi
2007	J	`jnl`	Simultaneous Reduction of Dynamic and Static Power in Scan Structures CoRR Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
2007	A	`conf`	Using the inter- and intra-switch regularity in NoC switch testing. DATE Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi
2006	—	`conf`	A New Protocol Stack Model for Network on Chip. ISVLSI Masood Deh-Yadegari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi
2006	J	`jnl`	A Test Approach for Look-Up Table Based FPGAs. J. Comput. Sci. Technol. Ehsan Atoofian, Zainalabedin Navabi
2006	A	`conf`	A concurrent testing method for NoC switches. DATE Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi
2006	—	`conf`	An Optimized BIST Architecture for FPGA Look-Up Table Testing. ISVLSI Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi
2006	—	`conf`	An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing. ATS Armin Alaghi, Mahnaz Sadoughi Yarandi, Zainalabedin Navabi
2006	—	`conf`	Ant colony based routing architecture for minimizing hot spots in NOCs. SBCCI Masoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi
2006	—	`conf`	ByZFAD: a low switching activity architecture for shift-and-add multipliers. SBCCI Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi
2006	C	`conf`	DCim++: a C++ library for object oriented hardware design and distributed simulation. ISCAS Hadi Esmaeilzadeh, A. Moghimi, Eiman Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie
2006	—	`conf`	ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs. ATS Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi
2006	C	`conf`	Low-power and low-latency cluster topology for local traffic NoCs. ISCAS Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
2006	—	`conf`	NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. ASAP Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi
2006	J	`jnl`	Scan-Based Structure with Reduced Static and Dynamic Power Consumption. J. Low Power Electron. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
2006	—	`conf`	Serial Bus Encoding for Low Power Application. SoC Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
2005	—	`conf`	A Flow Graph Technique for DFT Controller Modification. SoCC Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram A. Riahi, Fabrizio Lombardi, Zainalabedin Navabi
2005	—	`conf`	A low-power scan-path architecture. ISCAS (5) Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha
2005	Misc	`conf`	An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. VLSI Design Hamid Reza Ghasemi, Zainalabedin Navabi
2005	—	`conf`	Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. ISCAS (1) Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi
2005	C	`conf`	Combination of Assertion and HSAT Methods For Automated Test Vectors Generation. FDL Mostafa Naderi, Zainalabedin Navabi
2005	—	`book`	Digital design and implementation with field programmable devices. Zainalabedin Navabi
2005	—	`conf`	Enhancing Fault Simulation Performance by Dynamic Fault Clustering. Asian Test Symposium Shahrzad Mirkhani, Zainalabedin Navabi
2005	—	`conf`	ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. Asian Test Symposium Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi
2005	J	`jnl`	Instruction-level test methodology for CPU core self-testing. ACM Trans. Design Autom. Electr. Syst. Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi
2005	A*	`conf`	Sign bit reduction encoding for low power applications. DAC Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
2005	—	`conf`	Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. DFT Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi
2005	A	`conf`	Simultaneous Reduction of Dynamic and Static Power in Scan Structures. DATE Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
2005	—	`conf`	TED+: a data structure for microprocessor verification. ASP-DAC Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi
2004	J	`jnl`	A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. J. Electron. Test. Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin
2004	—	`conf`	Instruction level test methodology for CPU core software-based self-testing. HLDVT Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi
2004	—	`conf`	Property Checking based on Hierarchical Integer Equations. ACSD Bijan Alizadeh, Zainalabedin Navabi
2004	—	`conf`	Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. Asian Test Symposium Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi
2004	—	`conf`	Using Integer Equations to Check PSL Properties in RT Level Design. IWSOC Bijan Alizadeh, Zainalabedin Navabi
2004	J	`jnl`	Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. J. Electron. Test. Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi
2004	J	`jnl`	Using data compression in automatic test equipment for system-on-chip testing. IEEE Trans. Instrum. Meas. Farzin Karimi, Zainalabedin Navabi, Waleed Meleis, Fabrizio Lombardi
2003	—	`conf`	A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. Asian Test Symposium Ehsan Atoofian, Zainalabedin Navabi
2003	C	`conf`	A Low Power BIST Architecture for FPGA Look-Up Table Testing. VLSI-SOC Ehsan Atoofian, Zainalabedin Navabi
2003	Misc	`conf`	Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching. PDPTA Morteza Fayyazi, David R. Kaeli, Zainalabedin Navabi
2003	C	`conf`	Processor Testing Using an ADL Description and Genetic Algorithms. VLSI-SOC Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi
2003	—	`conf`	Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. DFT Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi
2003	C	`conf`	Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. VLSI-SOC Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi
2003	—	`conf`	The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. Asian Test Symposium Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi
2003	—	`conf`	Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment. Embedded Systems and Applications Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi
2003	—	`conf`	Utilizing Various ADL Facets for Instruction Level CPU Test. MTV Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi
2002	—	`conf`	Data Compression for System-on-Chip Testing Using ATE. DFT Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi
2002	—	`conf`	Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. Asian Test Symposium Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi
2001	A	`conf`	Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. DATE Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi
2001	—	`conf`	An efficient BIST method for testing of embedded SRAMs. ISCAS (5) Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie
2001	—	`conf`	Fault Simulation for VHDL Based Test Bench and BIST Evaluation. Asian Test Symposium Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi
1999	—	`ch.`	Hardware Description in Verilog. The VLSI Handbook Zainalabedin Navabi
1995	J	`jnl`	A Transistor Level Link for VHDL Simulation of VLSI Circuits. Simul. Zainalabedin Navabi, Zahra Razavi
1993	—	`conf`	Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models. CHDL Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai
1992	J	`jnl`	A high-level language for design and modeling of hardware. J. Syst. Softw. Zainalabedin Navabi
1991	J	`jnl`	Compiling gate Microprocess. Microsystems Zainalabedin Navabi
1991	J	`jnl`	Investigating simulation of hardware at various levels of abstraction and timing back-annotation of dataflow descriptions. Simul. Zainalabedin Navabi, Mehran Massoumi
1984	J	`jnl`	Hardware Compilation from an RTL to a Storage Logic Array Target. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fredrick J. Hill, Zainalabedin Navabi, Chen H. Chiang, Duan-Ping Chen, Manzer Masud
1981	J	`jnl`	Structure Specification with a Procedural Hardware Description Language. IEEE Trans. Computers Fredrick J. Hill, R. E. Swanson, Manzer Masud, Zainalabedin Navabi
1979	A*	`conf`	Efficient simulation of AHPL. DAC Zainalabedin Navabi, Fredrick J. Hill