Yvon Savaria - RankMe

473 papers A 12B 3C 83Misc 9Journal 170Unranked 192

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	IMICLiVAN: an improved method to increase cluster lifetime in vehicular ad hoc networks (VANETs). J. Supercomput. Erfan Moghadam, Elham Asghari, Seyed Amir Asghari, Mohammadreza Binesh Marvasti, Yvon Savaria
2026	J	`jnl`	Statistical Performance Analysis Framework for Bundled-Data Asynchronous Circuits With Dynamic Voltage Scaling. IET Comput. Digit. Tech. Maryem Benyoussef, Claude Thibeault, Yvon Savaria
2025	J	`jnl`	5G Fronthaul in Modular P4: eCPRI Protocol Processing and Precise BMv2 Timestamps for PTP-1588. IEEE Access Atabak Nojavan, Bill Pontikakis, François-Raymond Boyer, Yvon Savaria
2025	—	`conf`	A Comparative Analysis of Off-Policy DRL Strategies for Analog Circuit Optimization: A Case Study on Bandgap References. NewCAS Muhammed Abdelfatah, Ahmed Abuelnasr, Mostafa Amer, Yvon Savaria, Ahmad Hassan
2025	C	`conf`	A Prototyping Framework for P4-Programmable Traffic Managers. RSP Karl La Grassa, André Béliveau, Mathieu Léonardon, Jean-Pierre David, Matthieu Arzel, Yvon Savaria
2025	J	`jnl`	A Stateful Extension to P4THLS for Advanced Telemetry and Flow Control. Future Internet Mostafa Abbas Mollaei, Tarek Ould-Bachir, Yvon Savaria
2025	—	`conf`	AI-Assisted Design of a Compact Voltage Monitoring System with a Millisecond-Delayed Fault Detection Circuit. ICECS Ahmed Abuelnasr, Mostafa Amer, Isa H. Altoobaji, Ahmad Hassan, Yvon Savaria
2025	—	`conf`	Comparative Thermal Analysis of Single vs. Arrayed Layouts for Integrated Power Transistors Using COMSOL. ICECS Mostafa Amer, Ahmed Abuelnasr, Ahmad Hassan, Yvon Savaria
2025	J	`jnl`	Enabling Rank-Based P4 Programmable Schedulers: Requirements, Implementation, and Evaluation on BMv2 Switches. IEEE Trans. Netw. Mostafa Elbediwy, Bill Pontikakis, Jean-Pierre David, Yvon Savaria
2025	J	`jnl`	Long Short-Term Memory Neural Network Combined With a Hybrid-Modular Clockwork Structure for Transient Modeling of Nonlinear Circuits. IEEE Access Razieh Moradi Chaleshtori, Amin Saboohi, Amin Faraji, Sayed Alireza Sadrossadat, Ali Moftakharzadeh, Yvon Savaria
2025	J	`jnl`	P4Muse: Enabling Modular P4 Programming via Compiler-Managed Code Merging Without Syntax Modifications. IEEE Access Mohsen Rahmati, François-Raymond Boyer, Bill Pontikakis, Jean-Pierre David, Yvon Savaria
2025	J	`jnl`	P4THLS: A Templated HLS Framework to Automate Efficient Mapping of P4 Data-Plane Applications to FPGAs. IEEE Access Mostafa Abbas Mollaei, Tarek Ould-Bachir, Yvon Savaria
2025	J	`jnl`	Thermal Analysis of System in Package Considering Boundary Conditions for Long-Term Reliability Studies. IEEE Access Touati Djallel eddine, Aziz Oukaira, Ahmad Hassan, Mohamed Ali, Yvon Savaria, Ahmed Lakhssassi
2024	—	`conf`	$\mathcal{S}^{3}$1DCNN: A Compact Stacked Spectral-Spatial Attention 1DCNN for Seizure Prediction with Wearables. NewCAS Yang Zhang, Yvon Savaria, Mohamad Sawan, François Leduc-Primeau
2024	J	`jnl`	A 32-mV Supply Ring Oscillator Composed of Modified Schmitt Trigger Delay Cells for Integrated Start-Up Circuits in DC Energy Harvesting Systems. IEEE Access Mahmoud Ahmed, Aref Trigui, Sebastien Genevey, Yves Audet, Yvon Savaria
2024	—	`conf`	A Flexible Thermal/Solar Energy Harvesting System with Hysteretic Control and Maximum Power Point Tracking Regulation for IoT Devices. NewCAS Karim Kaced, Sebastien Genevey, Yvon Savaria, Jean-Pierre David
2024	J	`jnl`	A Systematic Approach for PLL-Based Zeta Power Converter Control. IEEE Access Nader El-Zarif, Christian Jesús B. Fayomi, Mohamed Ali, Mostafa Amer, Ahmad Hassan, Yvon Savaria
2024	J	`jnl`	Calibration of Ring Oscillator-Based Integrated Temperature Sensors for Power Management Systems. Sensors Nader El-Zarif, Mostafa Amer, Mohamed Ali, Ahmad Hassan, Aziz Oukaira, Christian Jesús B. Fayomi, Yvon Savaria
2024	—	`conf`	CoChrono: A Unified Hardware/Software Performance Analysis Tool for SoC-FPGA Codesign. NewCAS Fabien Portas, Guy Bois, Yvon Savaria
2024	J	`jnl`	DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue. IEEE Trans. Netw. Serv. Manag. Mostafa Elbediwy, Bill Pontikakis, Alireza Ghaffari, Jean-Pierre David, Yvon Savaria
2024	J	`jnl`	Digital Compensation of Timing Skew Mismatches in Time-Interleaved ADCs by Source Separation. IEEE Trans. Instrum. Meas. Hamidreza Mafi, Naim Ben-Hamida, Sadok Aouini, Yvon Savaria
2024	—	`conf`	Digital Compensation of Timing-Skew Mismatches in TI-ADCs by Modulation and Source Separation. NewCAS Hamidreza Mafi, Naim Ben-Hamida, Sadok Aouini, Yvon Savaria
2024	J	`jnl`	Enhanced Dynamic Regulation in Buck Converters: Integrating Input-Voltage Feedforward With Voltage-Mode Feedback. IEEE Access Mostafa Amer, Ahmed Abuelnasr, Mohamed Ali, Ahmad Hassan, Aref Trigui, Ahmed Ragab, Mohamad Sawan, Yvon Savaria
2024	B	`conf`	Enhancing P4 Syntax to Support Extended Finite State Machines as Native Stateful Objects. NetSoft Florent Allard, Tarek Ould-Bachir, Yvon Savaria
2024	J	`jnl`	Fast and Accurate Output Error Estimation for Memristor-Based Deep Neural Networks. IEEE Trans. Signal Process. Jonathan Kern, Sébastien Henwood, Gonçalo Mordido, Elsa Dupraz, Abdeldjalil Aïssa-El-Bey, Yvon Savaria, François Leduc-Primeau
2024	J	`jnl`	Incremental reinforcement learning for multi-objective analog circuit design acceleration. Eng. Appl. Artif. Intell. Ahmed Abuelnasr, Ahmed Ragab, Mostafa Amer, Benoit Gosselin, Yvon Savaria
2024	—	`conf`	MSPARQ: A RISC-V Vector Processor Array Optimized for Low-Resolution Neural Networks. MWSCAS Elisabeth Humblet, Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria
2024	—	`conf`	MemNAS: Super-net Neural Architecture Search for Memristor-based DNN Accelerators. SiPS Sébastien Henwood, Yvon Savaria, François Leduc-Primeau
2024	J	`jnl`	Nonlinear Circuit Macromodeling Using New Heterogeneous-Layered Deep Clockwork Recurrent Neural Network. IEEE Access Maedeh Azodi, Sayed Alireza Sadrossadat, Yvon Savaria
2024	—	`conf`	Normal and Resilient Mode FPGA-based Access Gateway Function Through P4-generated RTL. DRCN Mostafa Abbas Mollaei, Tarek Ould-Bachir, Yvon Savaria
2024	J	`jnl`	Novel Peak-Source-Scanning (NPSS) Model for Thermal Control of Systems-in-Package (SiP). IEEE Access Aziz Oukaira, Dhaou Said, Touati Djallel eddine, Nader El-Zarif, Ahmad Hassan, Yvon Savaria, Ahmed Lakhssassi
2024	J	`jnl`	Polara-Keras2c: Supporting Vectorized AI Models on RISC-V Edge Devices. IEEE Access Nizar El Zarif, MohammadHossein AskariHemmat, Théo Dupuis, Jean-Pierre David, Yvon Savaria
2024	J	`jnl`	PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA. Future Internet Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria
2024	J	`jnl`	QGen: On the Ability to Generalize in Quantization Aware Training. CoRR MohammadHossein AskariHemmat, Ahmadreza Jeddi, Reyhane Askari Hemmat, Ivan Lazarevich, Alexander Hoffman, Sudhakar Sah, Ehsan Saboori, Yvon Savaria, Jean-Pierre David
2024	—	`conf`	Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC. NewCAS Julien Posso, Guy Bois, Yvon Savaria
2024	J	`jnl`	Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC. CoRR Julien Posso, Guy Bois, Yvon Savaria
2024	J	`jnl`	Recent Start-Up Techniques Intended for TEG Energy Harvesting: A Review. IEEE Access Mahmoud Ahmed, Sebastien Genevey, Mohamed Ali, Yvon Savaria, Yves Audet
2024	—	`conf`	Sharpness-Aware Minimization Scaled by Outlier Normalization for Robust DNNs on In-Memory Computing Accelerators. IEEECONF Sébastien Henwood, Gonçalo Mordido, Yvon Savaria, Sarath Chandar, François Leduc-Primeau
2024	J	`jnl`	Spatial Registration of Heterogeneous Sensors on Mobile Platforms. IEEE Trans. Signal Process. Yajun Zeng, Jun Wang, Shaoming Wei, Jinping Sun, Peng Lei, Yvon Savaria, Chi Zhang
2024	J	`jnl`	Statistical Hardware Design With Multimodel Active Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alireza Ghaffari, Masoud Asgharian, Yvon Savaria
2024	C	`conf`	Utilization of Noise-Shaping in Mixed-Signal Timing-Skew Mismatch Calibration of TI-ADCs. ISCAS Hamidreza Mafi, Mohamed Amine Bensenouci, Sadok Aouini, Mohammad Honarparvar, Naim Ben-Hamida, Yvon Savaria
2023	J	`jnl`	A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. IEEE Access Mostafa Elbediwy, Bill Pontikakis, Jean-Pierre David, Yvon Savaria
2023	C	`conf`	An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs. ISCAS Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria
2023	J	`jnl`	An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform. IEEE Trans. Circuits Syst. II Express Briefs Hachem Bensalem, Yves Blaquière, Yvon Savaria
2023	—	`conf`	BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. ASP-DAC MohammadHossein AskariHemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David
2023	J	`jnl`	BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. CoRR MohammadHossein AskariHemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David
2023	—	`conf`	Background Calibration of Time-Interleaved ADCs with Polyphase Filters. NEWCAS Hamidreza Mafi, Mohamed Ali, Yvon Savaria, Mohammad Honarparvar, Naim Ben-Hamida
2023	J	`jnl`	Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. Ahmed Abuelnasr, Mostafa Amer, Mohamed Ali, Ahmad Hassan, Benoit Gosselin, Ahmed Ragab, Yvon Savaria
2023	—	`conf`	Enabling Human Activity Recognition in Smart Public Transportation Systems in Presence of Dataset Imbalance. ICECS Roya Alizadeh, Yvon Savaria, Chahé Nerguizian
2023	J	`jnl`	Enhanced Artificial Vision for Visually Impaired Using Visual Implants. IEEE Access Hossein Mahvash Mohammadi, Mohammad Hadi Edrisi, Yvon Savaria
2023	—	`conf`	High-Temperature Fully Integrated Wireless Monitoring Systems for Aerospace Applications. WiSEE Ahmad Hassan, Aref Trigui, Yvon Savaria, Mohamad Sawan
2023	—	`conf`	Implementing and Evaluating a P4-based Access Gateway Function on a Tofino Switch. CommNet El-Mehdi Makhroute, Mohammed-Ayoub Elharti, Vincent Brouillard, Yvon Savaria, Tarek Ould-Bachir
2023	—	`conf`	Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries. NEWCAS Dufour Jules, Yvon Savaria, Jean-Pierre David
2023	C	`conf`	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. ISCAS MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
2023	J	`jnl`	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. CoRR MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
2023	—	`conf`	Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference. NEWCAS Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, Nizar El Zarif, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria
2023	J	`jnl`	Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference. CoRR Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, Nizar El Zarif, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria
2023	J	`jnl`	Statistical Hardware Design With Multi-model Active Learning. CoRR Alireza Ghaffari, Masoud Asgharian, Yvon Savaria
2023	J	`jnl`	Symbolic Analysis for Data Plane Programs Specialization. ACM Trans. Archit. Code Optim. Thomas Luinaud, J. M. Pierre Langlois, Yvon Savaria
2022	J	`jnl`	A High-Sensitivity Wide Input-Power-Range Ultra-Low-Power RF Energy Harvester for IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Seyed Mohammad Noghabaei, Rafael L. Radin, Yvon Savaria, Mohamad Sawan
2022	J	`jnl`	A Hybrid Approach Based on Recurrent Neural Network for Macromodeling of Nonlinear Electronic Circuits. IEEE Access Amin Faraji, Sayed Alireza Sadrossadat, Mahdi Yazdian Dehkordi, Morteza Nabavi, Yvon Savaria
2022	J	`jnl`	A Molecular Imprinted PEDOT CMOS Chip-Based Biosensor for Carbamazepine Detection. IEEE Trans. Biomed. Circuits Syst. Abbas Hammoud, Hussein Assaf, Yvon Savaria, Dang Khoa Nguyen, Mohamad Sawan
2022	C	`conf`	A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing. ISCAS Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria
2022	J	`jnl`	A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges. IEEE Access Mohamed Ali, Ahmad Hassan, Mohammad Honarparvar, Morteza Nabavi, Yves Audet, Mohamad Sawan, Yvon Savaria
2022	C	`conf`	An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices. ISCAS Mengyue Su, Jean-Pierre David, Yvon Savaria, Bill Pontikakis, Thomas Luinaud
2022	—	`conf`	Automatic Detection of People Getting Into a Bus in a SMART Public Transportation System. ICECS 2022 Roya Alizadeh, Yvon Savaria, Chahé Nerguizian
2022	J	`jnl`	IBU: An In-Block Update Address Mapping Scheme for Solid-State Drives. IEEE Access Reza Gholami Taghizadeh, Mohammadreza Binesh Marvasti, Seyyed Amir Asghari, Ramin Gholami Taghizadeh, Morteza Nabavi, Yvon Savaria
2022	—	`conf`	Investigation of Different Integrated Temperature Monitoring Sensors for High-Voltage SoC DC-DC Converters. NEWCAS Nader El-Zarif, Mohamed Ali, Mostafa Amer, Ahmad Hassan, Aziz Oukaira, Ahmed Lakhssassi, Christian Jesús B. Fayomi, Yvon Savaria
2022	—	`conf`	Low Complexity Shallow Neural Network With Improved False Negative Rate for Cyber Intrusion Detection Systems. NEWCAS Jörg Ehmer, Bertrand Granado, Julien Denoulet, Yvon Savaria, Jean-Pierre David
2022	—	`conf`	MemSE: Fast MSE Prediction for Noisy Memristor-Based DNN Accelerators. AICAS Jonathan Kern, Sébastien Henwood, Gonçalo Mordido, Elsa Dupraz, Abdeldjalil Aïssa-El-Bey, Yvon Savaria, François Leduc-Primeau
2022	J	`jnl`	MemSE: Fast MSE Prediction for Noisy Memristor-Based DNN Accelerators. CoRR Jonathan Kern, Sébastien Henwood, Gonçalo Mordido, Elsa Dupraz, Abdeldjalil Aïssa-El-Bey, Yvon Savaria, François Leduc-Primeau
2022	C	`conf`	Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. ISCAS Julien Posso, Guy Bois, Yvon Savaria
2022	J	`jnl`	Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. CoRR Julien Posso, Guy Bois, Yvon Savaria
2022	J	`jnl`	Persistence Region Monitor With a Pheromone-Inspired Robot Swarm Sensor Network. IEEE Internet Things J. Yuzhan Wu, Meng Li, Guannan Li, Yvon Savaria
2022	J	`jnl`	QReg: On Regularization Effects of Quantization. CoRR MohammadHossein AskariHemmat, Reyhane Askari Hemmat, Alexander Hoffman, Ivan Lazarevich, Ehsan Saboori, Olivier Mastropietro, Yvon Savaria, Jean-Pierre David
2022	J	`jnl`	RLBEEP: Reinforcement-Learning-Based Energy Efficient Control and Routing Protocol for Wireless Sensor Networks. IEEE Access Ali Forghani Elah Abadi, Seyyed Amir Asghari, Mohammadreza Binesh Marvasti, Golnoush Abaei, Morteza Nabavi, Yvon Savaria
2022	J	`jnl`	Rethinking Pareto Frontier for Performance Evaluation of Deep Neural Networks. CoRR Vahid Partovi Nia, Alireza Ghaffari, Mahdi Zolnouri, Yvon Savaria
2022	—	`conf`	Tiny CNN for Seizure Prediction in Wearable Biomedical Devices. EMBC Yang Zhang, Yvon Savaria, Shiqi Zhao, Gonçalo Mordido, Mohamad Sawan, François Leduc-Primeau
2022	J	`jnl`	Towards Real-Time Monitoring of Thermal Peaks in Systems-on-Chip (SoC). Sensors Aziz Oukaira, Ahmad Hassan, Mohamed Ali, Yvon Savaria, Ahmed Lakhssassi
2021	C	`conf`	Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL. ISCAS Hachem Bensalem, Yves Blaquière, Yvon Savaria
2021	C	`conf`	Causal Information Prediction for Analog Circuit Design Using Variable Selection Methods Based on Machine Learning. ISCAS Ahmed Abuelnasr, Mostafa Amer, Ahmed Ragab, Benoit Gosselin, Yvon Savaria
2021	—	`conf`	Delay-Locked Loop Based Multiphase Clock Generator for Time-Interleaved ADCs. ICECS Ibrahim Alhousseiny, Mohamed Ali, Naim Ben-Hamida, Mohammad Honarparvar, Mohamad Sawan, Yvon Savaria
2021	A	`conf`	Design Principles for Packet Deparsers on FPGAs. FPGA Thomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria
2021	J	`jnl`	Design Principles for Packet Deparsers on FPGAs. CoRR Thomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria
2021	C	`conf`	Design and Analysis of Combined Input-Voltage Feedforward and PI Controllers for the Buck Converter. ISCAS Mostafa Amer, Ahmed Abuelnasr, Ahmed Ragab, Ahmad Hassan, Mohamed Ali, Benoit Gosselin, Mohamad Sawan, Yvon Savaria
2021	J	`jnl`	Efficient Design Space Exploration of OpenCL Kernels for FPGA Targets Using Black Box Optimization. IEEE Access Alireza Ghaffari, Yvon Savaria
2021	—	`conf`	Foster-based Transient Thermal Analysis of SiP for Thermomechanical Studies. NEWCAS Touati Djallel eddine, Aziz Oukaira, Ahmad Hassan, Yvon Savaria, Ahmed Lakhssassi
2021	—	`conf`	Human Activity Recognition and People Count for a SMART Public Transportation System. 5GWF Roya Alizadeh, Yvon Savaria, Chahé Nerguizian
2021	J	`jnl`	Introducing KeyRing self-timed microarchitecture and timing-driven design flow. IET Comput. Digit. Tech. Mickaël Fiorentino, Claude Thibeault, Yvon Savaria
2021	J	`jnl`	Multi-Sensor Track-to-Track Association and Spatial Registration Algorithm Under Incomplete Measurements. IEEE Trans. Signal Process. Jun Wang, Yajun Zeng, Shaoming Wei, Zixiang Wei, Qinchen Wu, Yvon Savaria
2021	—	`conf`	Non-parametric Statistical Static Timing Analysis based on Improved Parallel Monte Carlo. MWSCAS Zahra Qavamy, Behnam Ghavami, Morteza Nabavi, Yvon Savaria
2021	J	`jnl`	Power Bound Analysis of a Two-Step MASH Incremental ADC Based on Noise-Shaping SAR ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Masoume Akbari, Mohammad Honarparvar, Yvon Savaria, Mohamad Sawan
2021	C	`conf`	RISC-V Barrel Processor for Deep Neural Network Acceleration. ISCAS MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David
2021	J	`jnl`	Ring-Oscillator-Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. IEEE Trans. Instrum. Meas. Safa Berrima, Yves Blaquière, Yvon Savaria
2021	—	`conf`	Thermo-mechanical Analysis and Fatigue Life Prediction for Integrated Circuits (ICs). MWSCAS Aziz Oukaira, Touati Djallel eddine, Ahmad Hassan, Mohamed Ali, Yvon Savaria, Ahmed Lakhssassi
2020	—	`conf`	A 58 nW ± 35 ppm/°C Oscillator for IoT Battery-less Sensor Applications. ICECS Milad Salehi, Mohamed Ali, Yvon Savaria, Mohamad Sawan
2020	—	`conf`	A High Efficiency and Fast Response PLL Based Buck Converter: Implementation and Simulation. LASCAS Nader El-Zarif, Mohamed Ali, Ahmad Hassan, Morteza Nabavi, Christian Jesús B. Fayomi, Yvon Savaria
2020	J	`jnl`	A Real-Time Thermal Monitoring System Intended for Embedded Sensors Interfaces. Sensors Ouafaa Ettahri, Aziz Oukaira, Mohamed Ali, Ahmad Hassan, Morteza Nabavi, Yvon Savaria, Ahmed Lakhssassi
2020	—	`conf`	A VCO-Based Nonuniform Sampling ADC Using a Slope-Dependent Pulse Generator. ICM Mohamed Amine Bensenouci, Mohamed Ali, Hammoudi Escid, Yvon Savaria, Mohamad Sawan
2020	C	`conf`	Analog Circuits to Accelerate the Relaxation Process in the Equilibrium Propagation Algorithm. ISCAS Armin Najarpour Foroushani, Hussein Assaf, Fereidoon Hashemi Noshahr, Yvon Savaria, Mohamad Sawan
2020	C	`conf`	Bridging the Gap: FPGAs as Programmable Switches. HPSR Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois
2020	J	`jnl`	Bridging the Gap: FPGAs as Programmable Switches. CoRR Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois
2020	J	`jnl`	CNN2Gate: Toward Designing a General Framework for Implementation of Convolutional Neural Networks on FPGA. CoRR Alireza Ghaffari, Yvon Savaria
2020	J	`jnl`	Desynchronized Model Predictive Control for Large Populations of Fans in Server Racks of Datacenters. IEEE Trans. Smart Grid Gabriel Laparra, Meng Li, Guchuan Zhu, Yvon Savaria
2020	J	`jnl`	Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. IET Circuits Devices Syst. Safa Berrima, Yves Blaquière, Yvon Savaria
2020	J	`jnl`	Fully Integrated Digital GaN-Based LSK Demodulator for High-Temperature Applications. IEEE Trans. Circuits Syst. II Express Briefs Ahmad Hassan, Mostafa Amer, Yvon Savaria, Mohamad Sawan
2020	—	`conf`	Fully Integrated Dual-Channel Gate Driver and Area Efficient PID Compensator for Surge Tolerant Power Sensor Interface. NEWCAS Mostafa Amer, Mohamed Ali, Ahmed Abuelnasr, Ahmad Hassan, Morteza Nabavi, Yvon Savaria, Mohamad Sawan
2020	J	`jnl`	Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique. IEEE Trans. Circuits Syst. Aref Trigui, Mohamed Ali, Sami Hached, Jean-Pierre David, Ahmed Chiheb Ammari, Yvon Savaria, Mohamad Sawan
2020	J	`jnl`	In-FPGA Instrumentation Framework for OpenCL-Based Designs. IEEE Access Hachem Bensalem, Yves Blaquière, Yvon Savaria
2020	—	`conf`	Indoor Localization Using Channel State Information With Regression Artificial Neural Networks. VTC Spring Seyed Mohsen Samadani, Yvon Savaria, Chahé Nerguizian
2020	—	`conf`	Layerwise Noise Maximisation to Train Low-Energy Deep Neural Networks. AICAS Sébastien Henwood, François Leduc-Primeau, Yvon Savaria
2020	C	`conf`	OTA-Free MASH 2-2 Noise Shaping SAR ADC: System and Design Considerations. ISCAS Masoume Akbari, Mohammad Honarparvar, Yvon Savaria, Mohamad Sawan
2020	—	`conf`	OTA-Free MASH Two-Step Incremental ADC based on Noise Shaping SAR ADCs. NEWCAS Masoume Akbari, Mohammad Honarparvar, Yvon Savaria, Mohamad Sawan
2020	—	`ch.`	On the Use of Interval Arithmetic for the Branch and Bound Delta-Lognormal Parameter Extraction of Rapid Human Movements. The Lognormality Principle Simon Pierre Boyogueno Bidias, Jean-Pierre David, Yvon Savaria, Réjean Plamondon
2020	J	`jnl`	Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage. IEEE Trans. Very Large Scale Integr. Syst. Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
2020	Misc	`conf`	RISC-V Barrel Processor for Accelerator Control. FCCM MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David
2020	—	`conf`	SRAM Security and Vulnerability To Hardware Trojan: Design Considerations. MWSCAS Roghayeh Saeidi, Morteza Nabavi, Yvon Savaria
2020	C	`conf`	Self-Adjusting Deadtime Generator for High-Efficiency High-Voltage Switched-Mode Power Amplifiers. ISCAS Ahmed Abuelnasr, Mohamed Ali, Mostafa Amer, Morteza Nabavi, Ahmad Hassan, Benoit Gosselin, Yvon Savaria
2020	—	`conf`	Towards GaN500-based High Temperature ICs: Characterization and Modeling up to 600°C. NEWCAS Ahmad Hassan, Mostafa Amer, Yvon Savaria, Mohamad Sawan
2020	A	`conf`	Unleashing the Power of FPGAs as Programmable Switches. FPGA Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois
2019	J	`jnl`	A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. IEEE Trans. Very Large Scale Integr. Syst. Nicolas Laflamme-Mayer, Gilbert Kowarzyk, Yves Blaquière, Yvon Savaria, Mohamad Sawan
2019	J	`jnl`	A GaN-Based Wireless Monitoring System for High-Temperature Applications. Sensors Ahmad Hassan, Mohamed Ali, Aref Trigui, Yvon Savaria, Mohamad Sawan
2019	J	`jnl`	A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking. IEEE Access Imad Benacer, François-Raymond Boyer, Yvon Savaria
2019	C	`conf`	A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits. ISCAS Maryem Benyoussef, Claude Thibeault, Yvon Savaria
2019	—	`conf`	A Versatile SoC/SiP Sensor Interface for Industrial Applications: Design Considerations. ICM Mohamed Ali, Morteza Nabavi, Ahmad Hassan, Mohammad Honarparvar, Yvon Savaria, Mohamad Sawan
2019	—	`conf`	AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology. ASYNC Mickaël Fiorentino, Claude Thibeault, Yvon Savaria, François Gagnon, Tom Awad, Doug Morrissey, Michel Laurence
2019	C	`conf`	Bit-Slicing FPGA Accelerator for Quantized Neural Networks. ISCAS Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David
2019	J	`jnl`	Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs. Reliab. Eng. Syst. Saf. Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria
2019	J	`jnl`	Energy Efficient Generic Demodulator for High Data Transmission Rate Over an Inductive Link for Implantable Devices. IEEE Access Aref Trigui, Mohamed Ali, Ahmed Chiheb Ammari, Yvon Savaria, Mohamad Sawan
2019	J	`jnl`	Fast and Flexible Software Polar List Decoders. J. Signal Process. Syst. Mathieu Léonardon, Adrien Cassagne, Camille Leroux, Christophe Jégo, Louis-Philippe Hamelin, Yvon Savaria
2019	J	`jnl`	GaN-based LSK demodulators for wireless data receivers in high-temperature applications. Microelectron. J. Ahmad Hassan, Mohamed Ali, Yvon Savaria, Mohamad Sawan
2019	J	`jnl`	HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices. IEEE Access Imad Benacer, François-Raymond Boyer, Yvon Savaria
2019	J	`jnl`	Layerwise Noise Maximisation to Train Low-Energy Deep Neural Networks. CoRR Sébastien Henwood, François Leduc-Primeau, Yvon Savaria
2019	—	`conf`	Memristor Emulators for an Adaptive DPE Algorithm: Comparative Study. AICAS Hussein Assaf, Yvon Savaria, Mohamad Sawan
2019	J	`jnl`	Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. J. Electron. Test. Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
2019	J	`jnl`	SHIP: A Scalable High-Performance IPv6 Lookup Algorithm That Exploits Prefix Characteristics. IEEE/ACM Trans. Netw. Thibaut Stimpfling, Normand Bélanger, J. M. Pierre Langlois, Yvon Savaria
2019	J	`jnl`	Toward High-Performance Implementation of 5G SCMA Algorithms. IEEE Access Alireza Ghaffari, Mathieu Léonardon, Adrien Cassagne, Camille Leroux, Yvon Savaria
2019	C	`conf`	Toward In-System Monitoring of OpenCL-Based Designs on FPGA. ISCAS Hachem Bensalem, Yves Blaquière, Yvon Savaria
2019	J	`jnl`	Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-Trees (TDFTs). IEEE Access Marwan Ammar, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria
2019	—	`conf`	U-Net Fixed-Point Quantization for Medical Image Segmentation. LABELS/HAL-MICCAI/CuRIOUS@MICCAI MohammadHossein AskariHemmat, Sina Honari, Lucas Rouhier, Christian S. Perone, Julien Cohen-Adad, Yvon Savaria, Jean-Pierre David
2019	J	`jnl`	U-Net Fixed-Point Quantization for Medical Image Segmentation. CoRR MohammadHossein AskariHemmat, Sina Honari, Lucas Rouhier, Christian S. Perone, Julien Cohen-Adad, Yvon Savaria, Jean-Pierre David
2018	J	`jnl`	A 1.5-pJ/bit, 9.04-Mbit/s Carrier-Width Demodulator for Data Transmission Over an Inductive Link Supporting Power and Data Transfer. IEEE Trans. Circuits Syst. II Express Briefs Aref Trigui, Mohamed Ali, Ahmed Chiheb Ammari, Yvon Savaria, Mohamad Sawan
2018	J	`jnl`	A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Trans. Very Large Scale Integr. Syst. Imad Benacer, François-Raymond Boyer, Yvon Savaria
2018	C	`conf`	A High-Efficiency Ultra-Low-Power CMOS Rectifier for RF Energy Harvesting Applications. ISCAS Seyed Mohammad Noghabaei, Rafael L. Radin, Yvon Savaria, Mohamad Sawan
2018	J	`jnl`	A Hybrid Architecture With Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access Michel Gemieux, Meng Li, Yvon Savaria, Jean-Pierre David, Guchuan Zhu
2018	B	`conf`	A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis. CCGrid Thibaut Stimpfling, J. M. Pierre Langlois, Normand Bélanger, Yvon Savaria
2018	J	`jnl`	A pattern-based routing algorithm for a novel electronic system prototyping platform. Integr. Etienne Lepercq, Yves Blaquière, Yvon Savaria
2018	C	`conf`	Custom Low Power Processor for Polar Decoding. ISCAS Mathieu Léonardon, Camille Leroux, David Binet, J. M. Pierre Langlois, Christophe Jégo, Yvon Savaria
2018	C	`conf`	Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis. ISCAS Imad Benacer, François-Raymond Boyer, Yvon Savaria
2018	J	`jnl`	Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. Integr. Safa Berrima, Yves Blaquière, Yvon Savaria
2018	J	`jnl`	Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review. IEEE Trans. Very Large Scale Integr. Syst. Ahmad Hassan, Yvon Savaria, Mohamad Sawan
2018	J	`jnl`	Enhanced Bloom filter utilisation scheme for string matching using a splitting approach. IET Commun. Shervin Vakili, J. M. Pierre Langlois, Yvon Savaria, Naraig Manjikian
2018	Misc	`conf`	Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits. VTS Omar Al-Terkawi Hasib, Daniel Crepeau, Thomas Awad, Andrei Dulipovici, Yvon Savaria, Claude Thibeault
2018	—	`conf`	Extending a CPU Cache for Efficient IPv6 Lookup. MWSCAS Benjamin Wolff, Bachir Fradj, Normand Bélanger, Yvon Savaria
2018	J	`jnl`	Formal Dependability Modeling and Optimization of Scrubbed-Partitioned TMR for SRAM-based FPGAs. CoRR Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria
2018	J	`jnl`	GaN Integration Technology, an Ideal Candidate for High-Temperature Applications: A Review. IEEE Access Ahmad Hassan, Yvon Savaria, Mohamad Sawan
2018	—	`conf`	HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches. NEWCAS Imad Benacer, François-Raymond Boyer, Yvon Savaria
2018	J	`jnl`	Harvesting Energy From Aviation Data Lines: Implementation and Experimental Results. IEEE Trans. Circuits Syst. I Regul. Pap. Maryam Mohajertehrani, Yvon Savaria, Mohamad Sawan
2018	C	`conf`	High-Temperature Empirical Modeling for the I-V Characteristics of GaN150-Based HEMT. ISCAS Mostafa Amer, Ahmad Hassan, Ahmed Ragab, Soumaya Yacout, Yvon Savaria, Mohamad Sawan
2018	C	`conf`	High-Temperature Modeling of the I-V Characteristics of GaN150 HEMT Using Machine Learning Techniques. ISCAS Ahmed Abubakr, Ahmad Hassan, Ahmed Ragab, Soumaya Yacout, Yvon Savaria, Mohamad Sawan
2018	C	`conf`	Implementation of a Cache-Based IPv6 Lookup System with Hashing. ISCAS Bachir Fradj, Benjamin Wolff, Normand Bélanger, Yvon Savaria
2018	—	`conf`	Local Queueing-Based Data-Driven Task Scheduling for Multicore Systems. MWSCAS Meng Li, Chao Chen, Guchuan Zhu, Yvon Savaria
2018	J	`jnl`	New Insights Into Soft-Faults Induced Cardiac Pacemakers Malfunctions Analyzed at System-Level via Model Checking. IEEE Access Ghaith Bany Hamad, Marwan Ammar, Otmane Aït Mohamed, Yvon Savaria
2018	—	`conf`	Reliability Analysis of the SPARC V8 Architecture via Fault Trees and UPPAL-SMC. ICECS Marwan Ammar, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria
2018	—	`conf`	Transport Triggered Polar Decoders. ISTC Mathieu Léonardon, Camille Leroux, Pekka Jääskeläinen, Christophe Jégo, Yvon Savaria
2018	—	`conf`	Vector Matrix Multiplication Using Crossbar Arrays: A Comparative Analysis. ICECS Hussein Assaf, Yvon Savaria, Mohamad Sawan
2017	—	`conf`	A 14.5 µW generic Carrier Width demodulator for telemetry-based Medical Devices. NEWCAS Aref Trigui, Mohamed Ali, Ahmed Chiheb Ammari, Yvon Savaria, Mohamad Sawan
2017	C	`conf`	A Cache-Coherent Heterogeneous Architecture for Low Latency Real Time Applications. ISORC Michel Gemieux, Yvon Savaria, Jean-Pierre David, Guchuan Zhu
2017	J	`jnl`	A DAQM-Based Load Balancing Scheme for High Performance Computing Platforms. IEEE Access Kaijun Yang, Meng Li, Guchuan Zhu, Yvon Savaria
2017	—	`conf`	A data driven CGRA Overlay Architecture with embedded processors. NEWCAS Himan Khanzadi, Yvon Savaria, Jean-Pierre David
2017	—	`conf`	A high-speed traffic manager architecture for flow-based networking. NEWCAS Imad Benacer, François-Raymond Boyer, Yvon Savaria
2017	C	`conf`	A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array. ISCAS Safa Berrima, Yves Blaquière, Yvon Savaria
2017	—	`conf`	An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search. ACM Great Lakes Symposium on VLSI Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois
2017	A	`conf`	An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only). FPGA Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois
2017	—	`conf`	Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories. ACM Great Lakes Symposium on VLSI Ghaith Kazma, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria
2017	—	`conf`	Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories. NEWCAS Ghaith Kazma, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria
2017	C	`conf`	Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT. IOLTS Ghaith Bany Hamad, Ghaith Kazma, Otmane Aït Mohamed, Yvon Savaria
2017	J	`jnl`	Extensions to decision-tree based packet classification algorithms to address new classification paradigms. Comput. Networks Thibaut Stimpfling, Normand Bélanger, Omar Cherkaoui, André Béliveau, Ludovic Béliveau, Yvon Savaria
2017	—	`conf`	FPGA implementation of Token-based Self-timed processors: A case study. NEWCAS Mickaël Fiorentino, Yvon Savaria, Claude Thibeault
2017	J	`jnl`	Fast and Flexible Software Polar List Decoders. CoRR Mathieu Léonardon, Adrien Cassagne, Camille Leroux, Christophe Jégo, Louis-Philippe Hamelin, Yvon Savaria
2017	J	`jnl`	Formal Analysis of SEU Mitigation for Early Dependability and Performability Analysis of FPGA-based Space Applications. CoRR Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria
2017	J	`jnl`	Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits. J. Electron. Test. Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria
2017	J	`jnl`	Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications. J. Appl. Log. Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria
2017	—	`conf`	Improving performance of SCMA MPA decoders using estimation of conditional probabilities. NEWCAS Alireza Ghaffari, Mathieu Léonardon, Yvon Savaria, Christophe Jégo, Camille Leroux
2017	—	`conf`	Joint power control and beamformer design with antenna selection. CCECE Faika Hoque, Yvon Savaria, Christian Cardinal
2017	J	`jnl`	Reliability Enhancement of Redundancy Management in AFDX Networks. IEEE Trans. Ind. Informatics Meng Li, Guchuan Zhu, Yvon Savaria, Michaël Lauer
2017	J	`jnl`	SHIP: A Scalable High-performance IPv6 Lookup Algorithm that Exploits Prefix Characteristics. CoRR Thibaut Stimpfling, Normand Bélanger, J. M. Pierre Langlois, Yvon Savaria
2017	C	`conf`	Scalable memory-less architecture for string matching with FPGAs. ISCAS Ideh Sarbishei, Shervin Vakili, J. M. Pierre Langlois, Yvon Savaria
2017	—	`conf`	Stability of GaN150-based HEMT in high temperature up to 400°C. NEWCAS Ahmad Hassan, Mohamed Ali, Aref Trigui, Sami Hached, Yvon Savaria, Mohamad Sawan
2017	—	`conf`	Sub-ps resolution programmable delays implemented in a Xilinx FPGA. MWSCAS Safa Berrima, Yves Blaquière, Yvon Savaria
2016	C	`conf`	A compact spatially configurable differential input stage for a field programmable interconnection network. ISCAS Wasim Hussain, Yvon Savaria, Yves Blaquière
2016	—	`conf`	A fast systolic priority queue architecture for a flow-based Traffic Manager. NEWCAS Imad Benacer, François-Raymond Boyer, Normand Bélanger, Yvon Savaria
2016	J	`jnl`	A novel spatially configurable differential interface for an electronic system prototyping platform. Integr. Wasim Hussain, Olivier Valorge, Yves Blaquière, Yvon Savaria
2016	C	`conf`	A practical design method for prototyping self-timed processors using FPGAs. ISCAS Mickaël Fiorentino, Yvon Savaria, Claude Thibeault, Pascal Gervais
2016	J	`jnl`	An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform. IEEE Trans. Circuits Syst. I Regul. Pap. Wasim Hussain, Hussein Fakhoury, Patricia Desgreys, Yves Blaquière, Yvon Savaria
2016	—	`conf`	Applying formal verification to early assessment of FPGA-based aerospace applications: Methodology and experience. SysCon Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria
2016	C	`conf`	Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients. FDL Ghaith Bany Hamad, Ghaith Kazma, Otmane Aït Mohamed, Yvon Savaria
2016	—	`conf`	Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA. CCECE Fatima Zahra Tazi, Claude Thibeault, Yvon Savaria
2016	A	`conf`	Efficient and accurate analysis of single event transients propagation using SMT-based techniques. ICCAD Ghaith Bany Hamad, Ghaith Kazma, Otmane Aït Mohamed, Yvon Savaria
2016	—	`ch.`	Efficient identification of Faces in video Streams using low-Power Multi-Core Devices. Handbook of Pattern Recognition and Computer Vision Donavan Prieur, Eric Granger, Yvon Savaria, Claude Thibeault
2016	C	`conf`	Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking. FDL Marwan Ammar, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria
2016	—	`conf`	Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis. ICECS Ghaith Kazma, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria
2016	—	`conf`	Memory-Efficient String Matching for Intrusion Detection Systems using a High-Precision Pattern Grouping Algorithm. ANCS Shervin Vakili, J. M. Pierre Langlois, Bochra Boughzala, Yvon Savaria
2016	J	`jnl`	Monitoring Thermal Stress in Wafer-Scale Integrated Circuits by the Attentive Vision Method Using an Infrared Camera. IEEE Trans. Circuits Syst. Video Technol. Ahmed Lakhssassi, Roman Palenychka, Yvon Savaria, Michel Sayde, Marek B. Zaremba
2016	—	`conf`	Performance analysis of a reduced complexity SCMA decoder exploiting a low-complexity maximum-likelihood approximation. ICECS Roya Alizadeh, Yvon Savaria
2016	—	`conf`	Performance characterization of an SCMA decoder. NEWCAS Roya Alizadeh, Normand Bélanger, Yvon Savaria, François R. Boyer
2016	—	`conf`	Quad-Level Carrier Width Modulation demodulator for micro-implants. NEWCAS Aref Trigui, Mohamed Ali, Ahmed Chiheb Ammari, Yvon Savaria, Mohamad Sawan
2016	—	`conf`	Towards LTE physical layer virtualization on a COTS multicore platform with efficient scheduling. NEWCAS Michel Gemieux, Yvon Savaria, Guchuan Zhu, Jean-François Frigon
2016	C	`conf`	Towards efficient and concurrent FFTs implementation on Intel Xeon/MIC clusters for LTE and HPC. ISCAS Mounir Khelifi, Daniel Massicotte, Yvon Savaria
2016	C	`conf`	Towards formal abstraction, modeling, and analysis of Single Event Transients at RTL. ISCAS Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria
2016	Misc	`conf`	WeSPer: A flexible small delay defect quality metric. VTS Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
2016	C	`conf`	Wireless power transfer through metallic barriers enclosing a harsh environment; feasibility and preliminary results. ISCAS Ahmad Hassan, Aref Trigui, Umar Shafique, Yvon Savaria, Mohamad Sawan
2015	J	`jnl`	An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Wasim Hussain, Yves Blaquière, Yvon Savaria
2015	C	`conf`	Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms. ISCAS Pascal Nsame, Guy Bois, Yvon Savaria
2015	J	`jnl`	Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits. Microelectron. Reliab. Ghaith Bany Hamad, Syed Rafay Hasan, Otmane Aït Mohamed, Yvon Savaria
2015	—	`conf`	DPDK and MKL; Enabling technologies for near deterministic cloud-based signal processing. NEWCAS Roya Alizadeh, Normand Bélanger, Yvon Savaria, Jean-François Frigon
2015	C	`conf`	Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit. IOLTS Gontran Sion, Yves Blaquière, Yvon Savaria
2015	—	`ch.`	Design Intelligence for Interconnection Realization in Power-Managed SoCs. Computational Intelligence in Digital and Network Designs and Applications Houman Zarrabi, A. J. Al-Khalili, Yvon Savaria
2015	C	`conf`	Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients. IOLTS Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria
2015	—	`conf`	Harvesting energy from data lines for avionics applications: Power conversion chain architecture. ICM Maryam Mohajertehrani, Umar Shafique, Yvon Savaria, Mohamad Sawan
2015	—	`conf`	Mapping applications on two-level configurable hardware. AHS Himan Khanzadi, Yvon Savaria, Jean-Pierre David
2015	C	`conf`	Modeling the faulty behaviour of digital designs using a feed forward neural network approach. ISCAS Zeynab Mirzadeh, Jean-François Boland, Yvon Savaria
2015	—	`conf`	Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems. NORCAS Mounir Khelifi, Daniel Massicotte, Yvon Savaria
2015	—	`conf`	Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum. NEWCAS Hanieh Abdollahifakhr, Normand Bélanger, Yvon Savaria, François Gagnon
2015	—	`conf`	Self-timed circuits FPGA implementation flow. NEWCAS Mickaël Fiorentino, Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault
2015	A	`conf`	Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking. DATE Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria
2014	J	`jnl`	A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Nicolas Laflamme-Mayer, Yves Blaquière, Yvon Savaria, Mohamad Sawan
2014	—	`conf`	A Hausdorff Heuristic for Efficient Computation of Graph Edit Distance. S+SSPR Andreas Fischer, Réjean Plamondon, Yvon Savaria, Kaspar Riesen, Horst Bunke
2014	J	`jnl`	A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems. Circuits Syst. Signal Process. Qifeng Gan, J. M. Pierre Langlois, Yvon Savaria
2014	J	`jnl`	A computationally efficient importance sampling tracking algorithm. Mach. Vis. Appl. Rana Farah, Qifeng Gan, J. M. Pierre Langlois, Guillaume-Alexandre Bilodeau, Yvon Savaria
2014	—	`conf`	A current-output DAC for low-power low-noise log-domain ΔΣ modulators. NEWCAS Mohamed A. Shaheen, Anas A. Hamoui, Yvon Savaria
2014	—	`conf`	A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. ICECS Pascal Nsame, Guy Bois, Yvon Savaria
2014	—	`conf`	A memory transaction model for Sparse Matrix-Vector multiplications on GPUs. NEWCAS Thalie Keklikian, J. M. Pierre Langlois, Yvon Savaria
2014	C	`conf`	Abstracting Single Event Transient characteristics variations due to input patterns and fan-out. ISCAS Ghaith Bany Hamad, Syed Rafay Hasan, Otmane Aït Mohamed, Yvon Savaria
2014	—	`conf`	Adaptive real-time DSP acceleration for SoC applications. MWSCAS Pascal Nsame, Guy Bois, Yvon Savaria
2014	—	`conf`	Constraint-based configuration complexity model for autonomic network configuration management. GIIS Rudy Deca, Omar Cherkaoui, Yvon Savaria
2014	—	`conf`	Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications. NATW Pascal Nsame, Guy Bois, Yvon Savaria
2014	C	`conf`	Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain. ISCAS Yves Blaquière, Yan Basile-Bellavance, Safa Berrima, Yvon Savaria
2014	J	`jnl`	Determinism Enhancement of AFDX Networks via Frame Insertion and Sub-Virtual Link Aggregation. IEEE Trans. Ind. Informatics Meng Li, Michaël Lauer, Guchuan Zhu, Yvon Savaria
2014	J	`jnl`	Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations. J. Signal Process. Syst. Qifeng Gan, J. M. Pierre Langlois, Yvon Savaria
2014	—	`conf`	Modeling, analyzing, and abstracting single event transient propagation at gate level. MWSCAS Ghaith Bany Hamad, Syed Rafay Hasan, Otmane Aït Mohamed, Yvon Savaria
2014	B	`conf`	Neuromuscular Representation and Synthetic Generation of Handwritten Whiteboard Notes. ICFHR Andreas Fischer, Réjean Plamondon, Christian O'Reilly, Yvon Savaria
2014	J	`jnl`	On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations. CoRR Fatima Zahra Tazi, Claude Thibeault, Yvon Savaria, Simon Pichette, Yves Audet
2014	J	`jnl`	Optimizing the Parallel Tree-Search for Finding Shortest-Span Error-Correcting CDO Codes. IEEE Trans. Parallel Distributed Syst. Gilbert Kowarzyk, Normand Bélanger, David Haccoun, Yvon Savaria
2014	C	`conf`	Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications. MEMOCODE Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria, Claude Thibeault
2014	—	`conf`	Probabilistic model checking of single event transient propagation at RTL level. ICECS Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria
2014	—	`conf`	Vt-conscious repeater insertion in power-managed VLSI. ISIC Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria
2013	—	`conf`	A 2D Gaussian smoothing kernel mapped to heterogeneous platforms. NEWCAS Abdelaziz Trabelsi, Yvon Savaria
2013	J	`jnl`	A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design. J. Electron. Test. Claude Thibeault, Yassine Hariri, Syed Rafay Hasan, Christelle Hobeika, Yvon Savaria, Yves Audet, Fatima Zahra Tazi
2013	—	`conf`	A methodology for system-level fault injection based on gate-level faulty behavior. NEWCAS R. Robache, Jean-François Boland, Claude Thibeault, Yvon Savaria
2013	—	`conf`	A netlist pruning tool for an electronic system prototyping platform. NEWCAS Karim Baratli, Ahmed Lakhssassi, Yves Blaquière, Yvon Savaria
2013	—	`conf`	A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor. MWSCAS Qifeng Gan, J. M. Pierre Langlois, Yvon Savaria
2013	C	`conf`	A spatiotemporal attention operator for monitoring thermo-mechanical stress in wafer-scale integrated circuits using an infrared camera. ISPA Ahmed Lakhssassi, Roman Palenychka, Michel Sayde, Yvon Savaria, Marek B. Zaremba, Emmanuel Kengne
2013	—	`conf`	Accelerating a modified Gaussian pyramid with a customized processor. DASIP Diana Carolina Gil, J. M. Pierre Langlois, Yvon Savaria
2013	C	`conf`	An interface for the I ISCAS Wasim Hussain, Yvon Savaria, Yves Blaquière
2013	—	`conf`	Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking. FTSCS Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria, Claude Thibeault
2013	J	`jnl`	Efficient Parallel Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. IEEE Trans. Commun. Gilbert Kowarzyk, Normand Bélanger, David Haccoun, Yvon Savaria
2013	—	`conf`	Optimal packet classification applicable tothe OpenFlow context. HPPN@HPDC Thibaut Stimpfling, Yvon Savaria, André Béliveau, Normand Bélanger, Omar Cherkaoui
2013	—	`conf`	Software rendering methods to display wafer scale integrated circuit dataset. CCECE Mikael Guillemot, Yves Blaquière, Yvon Savaria
2012	J	`jnl`	A High-Efficiency Low-Voltage CMOS Rectifier for Harvesting Energy in Implantable Devices. IEEE Trans. Biomed. Circuits Syst. Saeid Hashemi, Mohamad Sawan, Yvon Savaria
2012	C	`conf`	A new approach for pin detection for an electronic system prototyping reconfigurable platform. RSP Hai H. Nguyen, Mikael Guillemot, Yvon Savaria, Yves Blaquière
2012	—	`conf`	A novel hybrid FIFO asynchronous clock domain crossing interfacing method. ACM Great Lakes Symposium on VLSI Zaid Al-bayati, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria
2012	—	`conf`	An FPGA compatible asynchronous wake-up receiver for Wireless Sensor Networks. NEWCAS Jean-François Pons, Jean-Jules Brault, Yvon Savaria
2012	J	`jnl`	Efficient Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. IEEE Trans. Commun. Gilbert Kowarzyk, N. Blanger, David Haccoun, Yvon Savaria
2012	C	`conf`	Identification of soft error glitch-propagation paths: Leveraging SAT solvers. ISCAS Ghaith Bany Hamad, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria
2012	J	`jnl`	Loop Acceleration Exploration for ASIP Architecture. IEEE Trans. Very Large Scale Integr. Syst. Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre
2012	—	`conf`	Optimal scheduling policy for AFDX End-Systems with virtual links of identical bandwidth allocation gap size. CCECE Romain Nishi, Guchuan Zhu, Yvon Savaria
2012	J	`jnl`	Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures. IEEE Trans. Very Large Scale Integr. Syst. Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria
2012	—	`conf`	Probabilistic model checking of clock domain crossing interfaces. NEWCAS Zaid Al-bayati, Otmane Aït Mohamed, Yvon Savaria, Mounir Boukadoum
2012	C	`conf`	Propagating analog signals through a fully digital network on an electronic system prototyping platform. ISCAS Omar Al-Terkawi Hasib, Walder Andre, Yves Blaquière, Yvon Savaria
2012	J	`jnl`	Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors. IEEE Trans. Very Large Scale Integr. Syst. P. Aubertin, J. M. Pierre Langlois, Yvon Savaria
2012	J	`jnl`	Rule-Based Network Service Provisioning. J. Networks Rudy Deca, Omar Cherkaoui, Yvon Savaria
2012	—	`conf`	State-holding free NULL Convention Logic™. MWSCAS Jean-François Pons, Jean-Jules Brault, Yvon Savaria
2012	—	`conf`	System modeling and multicore simulation using transactions. ICSAMOS Amine Anane, El Mostapha Aboulhamid, Yvon Savaria
2012	C	`conf`	Two-level configuration for FPGA: A new design methodology based on a computing fabric. ISCAS Mathieu Allard, Patrick Grogan, Yvon Savaria, Jean-Pierre David
2011	—	`conf`	A GPGPU-based software implementation of the PBDI deinterlacing algorithm. ICECS Gilbert Kowarzyk, Normand Bélanger, Yvon Savaria
2011	J	`jnl`	A Laser-Trimmed Rail-to-Rail Precision CMOS Operational Amplifier. IEEE Trans. Circuits Syst. II Express Briefs Rahul Singh, Yves Audet, Yves Gagnon, Yvon Savaria, Étienne Boulais, Michel Meunier
2011	J	`jnl`	A Low-Power Asynchronous Step-Down DC-DC Converter for Implantable Devices. IEEE Trans. Biomed. Circuits Syst. Omar Al-Terkawi Hasib, Mohamad Sawan, Yvon Savaria
2011	—	`conf`	A tracking algorithm suitable for embedded systems implementation. ICECS Rana Farah, Qifeng Gan, J. M. Pierre Langlois, Guillaume-Alexandre Bilodeau, Yvon Savaria
2011	—	`conf`	Activity management in battery-powered embedded systems: A case study of ZigBee® WSN. ICECS Houman Zarrabi, A. J. Al-Khalili, Yvon Savaria
2011	J	`jnl`	All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. Integr. Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad
2011	J	`jnl`	Analysis of Resistive Open Defects in Drowsy SRAM Cells. J. Electron. Test. Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria
2011	C	`conf`	Comparative analysis of contrast enhancement algorithms in surveillance imaging. ISCAS Diana Carolina Gil, Rana Farah, J. M. Pierre Langlois, Guillaume-Alexandre Bilodeau, Yvon Savaria
2011	—	`conf`	Customized embedded processor design for global photographic tone mapping. ICECS Shervin Vakili, Diana Carolina Gil, J. M. Pierre Langlois, Yvon Savaria, Guy Bois
2011	—	`conf`	Repeater insertion in power-managed VLSI systems. ACM Great Lakes Symposium on VLSI Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria
2011	—	`conf`	SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level. ICECS Ghaith Bany Hamad, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria
2010	—	`conf`	A spatially reconfigurable fast differential interface for a wafer scale configurable platform. ICECS Olivier Valorge, Yves Blaquière, Yvon Savaria
2010	C	`conf`	An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI. ISCAS Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria
2010	J	`jnl`	Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad
2010	J	`jnl`	Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad
2010	C	`conf`	Fully integrated ultra-low-power asynchronously driven step-down DC-DC converter. ISCAS Omar Al-Terkawi Hasib, Mohamad Sawan, Yvon Savaria
2010	J	`jnl`	Modeling R-2R Segmented-Ladder DACs. IEEE Trans. Circuits Syst. I Regul. Pap. David Marche, Yvon Savaria
2010	—	`conf`	Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit. ICECS Mohammed Bougataya, Oussama Berriah, Ahmed Lakhssassi, Adel-Omar Dahmane, Yves Blaquière, Yvon Savaria, Richard Norman, Richard Prytula
2009	—	`conf`	A low-area power-efficient CMOS active rectifier for wirelessly powered medical devices. ICECS Saeid Hashemi, Mohamad Sawan, Yvon Savaria
2009	J	`jnl`	A low-power 2GHz data conversion using delta modulation for portable application. Integr. Ali Naderi, Mohamad Sawan, Yvon Savaria
2009	J	`jnl`	A novel low-drop CMOS active rectifier for RF-powered devices: Experimental results. Microelectron. J. Saeid Hashemi, Mohamad Sawan, Yvon Savaria
2009	J	`jnl`	A very-high output impedance charge pump for low-voltage low-power PLLs. Microelectron. J. Louis-François Tanguay, Mohamad Sawan, Yvon Savaria
2009	C	`conf`	An All-digital Skew-adaptive Clock Scheduling Algorithm for Heterogeneous Multiprocessor Systems on Chips (MPSoCs). ISCAS Syed Rafay Hasan, Bill Pontikakis, Yvon Savaria
2009	J	`jnl`	An Improved Switch Compensation Technique for Inverted R-2R Ladder DACs. IEEE Trans. Circuits Syst. I Regul. Pap. David Marche, Yvon Savaria, Yves Gagnon
2009	—	`conf`	An interconnect-aware delay model for dynamic voltage scaling in NM technologies. ACM Great Lakes Symposium on VLSI Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria
2009	—	`conf`	Estimation of energy performance in computing platforms. ICECS Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria
2009	J	`jnl`	High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. J. Signal Process. Syst. Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
2009	J	`jnl`	Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. Trans. High Perform. Embed. Archit. Compil. Patrick Mahoney, Yvon Savaria, Guy Bois, Patrice Plante
2009	C	`conf`	Workflow for an Electronic Configurable Prototyping System. ISCAS Etienne Lepercq, Yves Blaquière, Richard Norman, Yvon Savaria
2008	—	`conf`	A very-high output impedance current mirror for very-low voltage biomedical analog circuits. APCCAS Louis-François Tanguay, Mohamad Sawan, Yvon Savaria
2008	J	`jnl`	Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. Hung Tien Bui, Yvon Savaria
2008	—	`conf`	Digital signal propagation on a wafer-scale smart active programmable interconnect. ICECS Olivier Valorge, Anh Tuan Nguyen, Yves Blaquière, Richard Norman, Yvon Savaria
2008	J	`jnl`	Guest Editorial: 20 Years of ASAP. J. Signal Process. Syst. Wayne Luk, Yvon Savaria, Oskar Mencer
2008	—	`conf`	Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL. ICECS Yan Basile-Bellavance, Etienne Lepercq, Yves Blaquière, Yvon Savaria
2008	J	`jnl`	Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC. IEEE Trans. Circuits Syst. I Regul. Pap. David Marche, Yvon Savaria, Yves Gagnon
2008	—	`conf`	Loop-oriented metrics for exploring an application-specific architecture design-space. ASAP Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre
2008	C	`conf`	Modeling and simulation of complex heterogeneous systems. ISCAS Amine Anane, El Mostapha Aboulhamid, Julie Vachon, Yvon Savaria
2008	J	`jnl`	On the Design of Undersampling Continuous-Time Bandpass Delta-Sigma Modulators for Gigahertz Frequency A/D Conversion. IEEE Trans. Circuits Syst. I Regul. Pap. Ali Naderi, Mohamad Sawan, Yvon Savaria
2008	J	`jnl`	Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter. IEEE Trans. Instrum. Meas. Max-Elie Salomon, Badre Izouggaghen, Abdelhakim Khouas, Yvon Savaria
2007	J	`jnl`	A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion. IEEE Trans. Consumer Electron. Hossein Mahvash Mohammadi, J. M. Pierre Langlois, Yvon Savaria
2007	C	`conf`	A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. ISCAS Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria
2007	—	`conf`	A Methodology to Evaluate the Energy Efficiency of Application Specific Processors. ICECS Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
2007	J	`jnl`	A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration. J. VLSI Signal Process. Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre
2007	J	`jnl`	A high-level requirements engineering methodology for electronic system-level design. Comput. Electr. Eng. Nicolas Gorse, P. Bélanger, Alexandre Chureau, El Mostapha Aboulhamid, Yvon Savaria
2007	—	`conf`	An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept. ICECS Karim Hadjiat, Francis St-Pierre, Guy Bois, Yvon Savaria, Michel Langevin, Pierre G. Paulin
2007	J	`jnl`	Constraint-based model for network service provisioning. Ann. des Télécommunications Rudy Deca, Omar Cherkaoui, Yvon Savaria, Doug Slone
2007	C	`conf`	Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology. ISCAS Syed Rafay Hasan, Yvon Savaria
2007	—	`conf`	Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os. ICECS Yves Blaquière, Yvon Savaria, Jaouad El Fouladi
2007	C	`conf`	High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique. ISCAS Robert Chebli, Mohamad Sawan, Yvon Savaria, Kamal El-Sankary
2007	C	`conf`	Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier. ISCAS Rahul Singh, Yves Audet, Yves Gagnon, Yvon Savaria
2007	—	`conf`	Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis. ICECS Abdelaziz Trabelsi, François-Raymond Boyer, Yvon Savaria, Mounir Boukadoum
2007	C	`conf`	Modeling the Substrate Noise Injected by a DC-DC Converter. ISCAS Vincent Binet, Yvon Savaria, Michel Meunier, Yves Gagnon
2007	—	`conf`	New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches. ICECS Abdessatar Abderrahman, Mohamad Sawan, Yvon Savaria, Abdelhakim Khouas
2007	—	`conf`	Signal Integrity Analysis of a High Precision D/A Converter. ICECS Olivier Valorge, David Marche, Alain Lacourse, Mohamad Sawan, Yvon Savaria
2006	C	`conf`	A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. ISCAS Bill Pontikakis, François R. Boyer, Yvon Savaria
2006	J	`jnl`	A Metric for Automatic Word-Length Determination of Hardware Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie
2006	—	`conf`	A Threshold-Based Deinterlacing Algorithm Using Motion Compensation and Directional Interpolation. ICECS Hossein Mahvash Mohammadi, J. M. Pierre Langlois, Yvon Savaria
2006	C	`conf`	A novel 2-GHz band-pass delta modulator dedicated to wireless receivers. ISCAS Ali Naderi, Mohamad Sawan, Yvon Savaria
2006	C	`conf`	A power planning model for implantable stimulators. ISCAS Saeid Hashemi, Mohamad Sawan, Yvon Savaria
2006	C	`conf`	Architecture of a hypertransport tunnel. ISCAS Ami Castonguay, Yvon Savaria
2006	C	`conf`	Design exploration with an application-specific instruction-set processor for ELA deinterlacing. ISCAS Maria Mbaye, D. Lebel, Normand Bélanger, Yvon Savaria, Samuel Pierre
2006	—	`conf`	Design of an Active-RC Bandpass Filter for a Subsampling RF Delta Modulator. CCECE Ali Naderi, Mohamad Sawan, Yvon Savaria
2006	—	`conf`	Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. DELTA Abdelaziz Ammari, Régis Leveugle, Bogdan Nicolescu, Yvon Savaria
2006	—	`conf`	High speed differential pulse-width control loop based on frequency-to-voltage converters. ACM Great Lakes Symposium on VLSI Hung Tien Bui, Yvon Savaria
2006	C	`conf`	High-voltage operational amplifier based on dual floating-gate transistors. ISCAS Z. Huang, Yvon Savaria, Mohamad Sawan, R. Meinga
2006	—	`conf`	Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. SiPS Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
2006	A	`conf`	Soft-error classification and impact analysis on real-time operating systems. DATE N. Ignat, Bogdan Nicolescu, Yvon Savaria, Gabriela Nicolescu
2006	—	`conf`	Validation by Fault Injection of a Software Error Detection Technique Dealing with Critical Single Event Upsets. LATW S. Torrellas, Bogdan Nicolescu, Raul Velazco, Mario García-Valderas, Yvon Savaria
2006	C	`conf`	Zero skew differential clock distribution network. ISCAS Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria
2005	—	`conf`	. A new switch compensation technique for inverted R-2R ladder DACs. ISCAS (1) David Marche, Yves Gagnon, Yvon Savaria
2005	—	`conf`	A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs. IWSOC Hung Tien Bui, Yvon Savaria
2005	C	`conf`	A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemC. IEEE International Workshop on Rapid System Prototyping Ami Castonguay, Yvon Savaria
2005	—	`conf`	A complete spurs distribution model for direct digital period synthesizers. ISCAS (5) Max-Elie Salomon, Abdelhakim Khouas, Yvon Savaria
2005	—	`conf`	A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms. ISCAS (4) Alexandre Landry, Mohamed Nekili, Yvon Savaria
2005	—	`conf`	A novel approach for implementing ultra-high speed flash ADC using MCML circuits. ISCAS (6) Dinh Hung Dang, Yvon Savaria, Mohamad Sawan
2005	J	`jnl`	A system level implementation strategy and partitioning heuristic for LUT-based applications. Comput. Electr. Eng. Hakim Khali, Yvon Savaria, Jean-Louis Houle
2005	—	`conf`	Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. ISQED Wei Ling, Yvon Savaria
2005	—	`conf`	Application specific instruction-set processor generation for video processing based on loop optimization. ISCAS (4) Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre
2005	—	`conf`	Characterization of laser-induced photoexcitation effect on a surrounding CMOS ring oscillator. ISCAS (4) Guillaume Wild, Yvon Savaria, Michel Meunier
2005	—	`conf`	Component-Based Methodology for Hardware Design of a Dataflow Processing Network. IWSOC Robert Grou-Szabo, Hany Ghattas, Yvon Savaria, Gabriela Nicolescu
2005	—	`conf`	Design methods for CMOS low-current finely tunable voltage references covering a wide output range. ISCAS (5) Simon Rioux, Alain Lacourse, Yvon Savaria, Michel Meunier
2005	—	`conf`	Fast parameters optimization of an iterative decoder using a configurable hardware accelerator. ISCAS (4) G. Provost, Marc-André Cantin, Mohamad Sawan, Christian Cardinal, Yvon Savaria, David Haccoun
2005	—	`conf`	Gate oxide protection in HV CMOS/DMOS integrated circuits: Design and experimental results. ICECS Robert Chebli, Mohamad Sawan, Yvon Savaria
2005	—	`conf`	Implementation of a cycle by cycle variable speed processor. ISCAS (4) H. G. Epassa, François R. Boyer, Yvon Savaria
2005	—	`conf`	Modeling power budget requirements of implantable electronic devices. ICECS Saeid Hashemi, Mohamad Sawan, Yvon Savaria
2005	—	`conf`	Parameters estimation applied to automatic video processing algorithms validation. ISCAS (4) S. Catudal, Marc-André Cantin, Yvon Savaria
2005	—	`conf`	Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. IWSOC Bill Pontikakis, François R. Boyer, Yvon Savaria
2005	J	`jnl`	Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. ACM Trans. Design Autom. Electr. Syst. Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria
2005	A	`conf`	The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application. DATE Alexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid
2004	—	`conf`	10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. IWSOC Hung Tien Bui, Yvon Savaria
2004	—	`conf`	A Customizable Embedded SoC Platform Architecture. IWSOC Pascal Nsame, Yvon Savaria
2004	—	`conf`	A Framework for Implementing Reusable Digital Signal Processing Modules. IWSOC L.-P. Lafrance, Yvon Savaria
2004	J	`jnl`	A Unified Environment to Assess Image Quality in Video Processing. J. Circuits Syst. Comput. Marc-André Cantin, S. Regimbal, S. Catudal, Yvon Savaria
2004	—	`conf`	An ADPLL circuit using a DDPS for genlock applications. ISCAS (4) Dorin Emil Calbaza, Ioan Cordos, Nigel Seth-Smith, Yvon Savaria
2004	—	`conf`	An Integrated Test Platform for Nanostructure Electrical Characterization. ICMENS Olivier Duval, L.-P. Lafrance, Yvon Savaria, Patrick Desjardins
2004	—	`conf`	An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters. IWSOC D. Morin, Frédéric Normandin, Marie-Eve Grandmaison, H. Dang, Yvon Savaria, Mohamad Sawan
2004	—	`conf`	An on-chip delay measurements module for nanostructures characterization. ISCAS (3) Olivier Duval, Yvon Savaria
2004	—	`conf`	Assertion-based on-line verification and debug environment for complex hardware systems. ISCAS (2) Kevin Peterson, Yvon Savaria
2004	—	`conf`	Interface-based Design of Systems-on-Chip using UML-RT. IWSOC Alexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid
2004	—	`conf`	Multi-processor SoC integration: a case study on BlueGene/L. SoCC Pascal Nsame, Yvon Savaria
2004	C	`conf`	Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique. IOLTS Bogdan Nicolescu, Yvon Savaria, Raoul Velazco
2004	—	`conf`	Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. ISCAS (4) Hung Tien Bui, Yvon Savaria
2004	—	`conf`	Spurs modeling in direct digital period synthesizers related to phase accumulator truncation. ISCAS (3) Badre Izouggaghen, Abdelhakim Khouas, Yvon Savaria
2004	—	`conf`	The Effect of p-Coupling on the Electronic Properties of 1, 4-Dithiol Benzene Stacking. ICMENS Mohammed Layachi, Yvon Savaria, Alain Rochefort
2004	—	`conf`	Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. IWSOC S. Regimbal, Yvon Savaria, Guy Bois
2003	—	`conf`	A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement. ISCAS (3) Mathieu Renaud, Yvon Savaria
2003	J	`jnl`	A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning. IEEE Trans. Pattern Anal. Mach. Intell. Eric Granger, Yvon Savaria, Pierre Lavoie
2003	—	`conf`	A hardware-software co-design model for real-time 3D image computation using active laser range finders: a case study. ICECS Hakim Khali, Yvon Savaria
2003	—	`conf`	A new memory reference reduction method for FFT implementation on DSP. ISCAS (4) Yiyan Tang, Lie Qian, Yuke Wang, Yvon Savaria
2003	—	`conf`	Automating Functional Coverage Analysis Based on an Executable Specification. IWSOC S. Regimbal, Jean-Francois Lemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid, A. Baron
2003	—	`conf`	Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study. DFT Bogdan Nicolescu, Paul Peronnard, Raoul Velazco, Yvon Savaria
2003	—	`conf`	IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration. DFT Meng Lu, Yvon Savaria, Bing Qiu, Jacques Taillefer
2003	J	`jnl`	Improvement of sensor accuracy in the case of a variable surface reflectance gradient for active laser range finders. IEEE Trans. Instrum. Meas. Hakim Khali, Yvon Savaria, Jean-Louis Houle, Marc Rioux, J.-Angelo Beraldin, D. Poussart
2003	J	`jnl`	Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria
2003	—	`conf`	SIED: Software Implemented Error Detection. DFT Bogdan Nicolescu, Yvon Savaria, Raoul Velazco
2003	—	`conf`	SoC platform architecture for a network processor. SoC Hany Ghattas, M. Mbaye, J. Pepga Bissou, Yvon Savaria
2003	—	`conf`	Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. ACM Great Lakes Symposium on VLSI Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria
2002	—	`conf`	A CMOS phase-locked loop with an auto-calibrated VCO. ISCAS (3) Youcef Fouzar, Yvon Savaria, Mohamad Sawan
2002	J	`jnl`	A direct digital period synthesis circuit. IEEE J. Solid State Circuits Dorin Emil Calbaza, Yvon Savaria
2002	A	`conf`	A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs. FPGA J. Dido, N. Géraudie, L. Loiseau, O. Payeur, Yvon Savaria, D. Poirier
2002	—	`conf`	A linear phase detector for arbitrary clock signals. ISCAS (4) Mathieu Renaud, Yvon Savaria
2002	J	`jnl`	A practical approach to model long MIS interconnects in VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. Zhong-Fang Jin, Jean-Jacques Laurin, Yvon Savaria
2002	—	`conf`	Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm. ISCAS (4) L.-P. Lafrance, Marc-André Cantin, Yvon Savaria, S. H. Sung, Pierre Lavoie
2002	Misc	`conf`	FPGA Implementation of a Sub-pixel Correction Algorithm for Active Laser Range Finders. MVA Hakim Khali, Yvon Savaria
2002	—	`conf`	Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique. ISCAS (3) A. Bendali, Yvon Savaria
2002	—	`conf`	Yield Modeling of a WSI Telecom Router Architecture. DFT Bing Qiu, Yvon Savaria, Meng Lu, Chunyan Wang, Claude Thibeault
2001	—	`conf`	A new controlled gain phase-locked loop technique. ISCAS (4) Youcef Fouzar, Yvon Savaria, Mohamad Sawan
2001	—	`conf`	An automatic word length determination method. ISCAS (5) Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie
2001	C	`conf`	Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages. ICCD Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria
2001	J	`jnl`	Direct digital frequency synthesis of low-jitter clocks. IEEE J. Solid State Circuits Dorin Emil Calbaza, Yvon Savaria
2001	—	`conf`	Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques. ISSS Noureddine Chabini, Yvon Savaria
2001	—	`conf`	Minimizing process-induced skew using delay tuning. ISCAS (4) Mohamed Nekili, Yvon Savaria, Guy Bois
2001	J	`jnl`	Optimal design of synchronous circuits using software pipelining techniques. ACM Trans. Design Autom. Electr. Syst. François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer
2001	—	`conf`	Performance estimators for hardware/software co-design. ISCAS (5) Lévis Thériault, Daniel Audet, Yvon Savaria
2001	Misc	`conf`	Tools for the Characterization of Bipolar CML Testability. VTS Ginette Monté, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst
2000	—	`conf`	A method to derive application-specific embedded processing cores. CODES Olivier Hébert, Ivan C. Kraljic, Yvon Savaria
2000	C	`conf`	A methodology for validating digital circuits with mutation testing. ISCAS Patrice Vado, Yvon Savaria, Yannick Zoccarato, Chantal Robach
2000	C	`conf`	A new fully integrated CMOS phase-locked loop with low jitter and fast lock time. ISCAS Youcef Fouzar, Mohamad Sawan, Yvon Savaria
2000	—	`conf`	An efficient verification method for a class of multi-phase sequential circuits. ICECS François-Raymond Boyer, El Mostapha Aboulhamid, Yvon Savaria
2000	C	`conf`	Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm. ISCAS Marc-André Cantin, Yves Blaquière, Yvon Savaria, Pierre Lavoie, Eric Granger
2000	—	`conf`	Direct digital frequency synthesis of low-jitter clocks. CICC Dorin Emil Calbaza, Yvon Savaria
2000	—	`conf`	Very short locking time PLL based on controlled gain technique. ICECS Youcef Fouzar, Mohamad Sawan, Yvon Savaria
1999	—	`conf`	A new approach to analyze interconnect delays in RC wire models. ISCAS (6) Zhong-Fang Jin, Jean-Jacques Laurin, Yvon Savaria, Pierre Garon
1999	A	`conf`	Design For Testability Method for CML Digital Circuits. DATE Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham
1999	Misc	`conf`	Design of a JTAG Based Run Time Reconfigurable System. FCCM Cynthia Cousineau, François Laperle, Yvon Savaria
1999	—	`conf`	Development of a high performance TSPC library for implementation of large digital building blocks. ISCAS (1) B. Le Chapelain, A. Mechain, Yvon Savaria, Guy Bois
1999	J	`jnl`	Generalization, discrimination, and multiple categorization using adaptive resonance theory. IEEE Trans. Neural Networks Pierre Lavoie, Jean-François Crespo, Yvon Savaria
1999	—	`conf`	Jitter model of direct digital synthesis clock generators. ISCAS (1) Dorin Emil Calbaza, Yvon Savaria
1999	J	`jnl`	Reconfigurable pipelined 2-D convolvers for fast digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. B. Bosi, Guy Bois, Yvon Savaria
1999	J	`jnl`	Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI. IEEE J. Solid State Circuits Mohamed Nekili, Yvon Savaria, Guy Bois
1998	Misc	`conf`	A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing. FCCM Pascal Poiré, Marc-André Cantin, Hervé Daniel, Yves Blaquière, Yvon Savaria
1998	J	`jnl`	A comparison of self-organizing neural networks for fast clustering of radar pulses. Signal Process. Eric Granger, Yvon Savaria, Pierre Lavoie, Marc-André Cantin
1998	—	`conf`	Design of Clock Distribution Networks in Presence of Process Variations. Great Lakes Symposium on VLSI Mohamed Nekili, Yvon Savaria, Guy Bois
1998	C	`conf`	Optimal design of synchronous circuits using software pipelining techniques. ICCD François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Imed Eddine Bennour
1998	C	`conf`	Parallel ultra large scale engine SIMD architecture for real-time digital signal processing applications. ICCD Paul Marriott, Ivan C. Kraljic, Yvon Savaria
1998	—	`conf`	Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure. DFT Daniel Audet, Steve Masson, Yvon Savaria
1997	—	`conf`	A Cost Model for VLSI / MCM Systems. DFT Michel Kafrouni, Claude Thibeault, Yvon Savaria
1997	—	`conf`	Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. DFT Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault
1997	—	`conf`	Multiple categorization using fuzzy ART. ICNN Pierre Lavoie, Jean-François Crespo, Yvon Savaria
1997	J	`jnl`	Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Trans. Very Large Scale Integr. Syst. Mohamed Nekili, Guy Bois, Yvon Savaria
1996	Misc	`conf`	Design and performance of CMOS TSPC cells for high speed pseudo random testing. VTS Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska
1996	—	`conf`	Implementing Fault Injection and Tolerance Mechanisms in Multiprocessor Systems. DFT Daniel Audet, N. Gagnon, Yvon Savaria
1996	J	`jnl`	Panel Summaries. IEEE Des. Test Comput. Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov
1996	J	`jnl`	Reconstruction method for jitter tolerant data acquisition system. J. Electron. Test. Adel Belhaouane, Yvon Savaria, Bozena Kaminska, Daniel Massicotte
1996	J	`jnl`	Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yves Blaquière, Michel R. Dagenais, Yvon Savaria
1995	—	`conf`	A new method for testing mixed analog and digital circuits. Asian Test Symposium Janusz Rzeszut, Bozena Kaminska, Yvon Savaria
1995	J	`jnl`	Bounds on the performance of partial selection networks. IEEE Trans. Commun. Jean Belzile, Yvon Savaria, David Haccoun, Martin Chalifoux
1995	—	`conf`	Cost analysis of a new algorithmic-based soft-error tolerant architecture. DFT Yves Blaquière, Gabriel Gagné, Yvon Savaria, Claude Évéquoz
1995	J	`jnl`	Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits. IEEE Trans. Computers Claude Thibeault, Yvon Savaria, Jean-Louis Houle
1995	C	`conf`	On Using Partial Reset for Pseudo-Random Testing. ISCAS Mohamed Soufi, Yvon Savaria, Bozena Kaminska
1995	Misc	`conf`	On the design of at-speed testable VLSI circuits. VTS Mohamed Soufi, Yvon Savaria, Bozena Kaminska
1995	J	`jnl`	Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors. IEEE Trans. Computers Mohamed Soufi, Yvon Savaria, F. Darlay, Bozena Kaminska
1994	C	`conf`	A Comparative Study of Single-Phase Clocked Latches Using Estimation Criteria. ISCAS Sameh Ghannoum, Dmitri Chtchvyrkov, Yvon Savaria
1994	C	`conf`	A Fast CMOS Voltage-Controlled Ring Oscillator. ISCAS Yvon Savaria, Dmitri Chtchvyrkov, John F. Currie
1994	C	`conf`	A Fast Low-Power Driver for Long Interconnections in VLSI Systems. ISCAS Mohamed Nekili, Yvon Savaria, Guy Bois
1994	J	`jnl`	A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits. IEEE Trans. Computers Claude Thibeault, Yvon Savaria, Jean-Louis Houle
1994	J	`jnl`	A multiprocessor architecture for multiple path stack sequential decoders. IEEE Trans. Commun. Normand Bélanger, David Haccoun, Yvon Savaria
1994	J	`jnl`	A systolic architecture for fast stack sequential decoders. IEEE Trans. Commun. Pierre Lavoie, David Haccoun, Yvon Savaria
1994	—	`conf`	Defect and Fault Tolerant Scan Chains. DFT Rachid Kermouche, Yvon Savaria
1994	—	`conf`	Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits. EDAC-ETC-EUROASIC Abdessatar Abderrahman, Bozena Kaminska, Yvon Savaria
1994	C	`conf`	Fast Convergence with Low Precision Weights in ART1 Networks. ISCAS Jean-François Crespo, Pierre Lavoie, Yvon Savaria
1994	J	`jnl`	Pipelining communications in large VLSI/ULSI systems. IEEE Trans. Very Large Scale Integr. Syst. Daniel Audet, Yvon Savaria, N. Arel
1994	C	`conf`	Pseudo-Random Vector Compaction for Sequential Testability. ISCAS Naim Ben-Hamida, Bozena Kaminska, Yvon Savaria
1993	C	`conf`	A High Speed Parallel Structure for the Basic Wavelet Transform Algorithm. ISCAS Hakim Khali, Jean-Louis Houle, Yvon Savaria
1993	C	`conf`	Initiability: A Measure of Sequential Testability. ISCAS Naim Ben-Hamida, Bozena Kaminska, Yvon Savaria
1993	C	`conf`	Parallel Regeneration of Interconnections in VLSI & ULSI Circuits. ISCAS Mohamed Nekili, Yvon Savaria
1993	—	`conf`	Some Results on Yield and Local Design Rule Relaxation. DFT J. Crépeau, Claude Thibeault, Yvon Savaria
1993	—	`ed.`	The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 27-29, 1993, Venice, Italy, Proceedings DFT Fabrizio Lombardi, Mariagiovanna Sami, Yvon Savaria, Renato Stefanelli
1992	J	`jnl`	Heuristic Prediction of the Optimum Number of spares in Defect-Tolerant Integrated Circuits. J. Circuits Syst. Comput. Claude Thibeault, Yvon Savaria, Jean-Louis Houle
1992	J	`jnl`	Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources. Parallel Comput. Daniel Audet, Yvon Savaria, Jean-Louis Houle
1992	J	`jnl`	Test quality of hierarchical defect-tolerant integrated circuits. J. Electron. Test. Claude Thibeault, Yvon Savaria, Jean-Louis Houle
1991	J	`jnl`	New VLSI architectures for fast soft-decision threshold decoders. IEEE Trans. Commun. Pierre Lavoie, David Haccoun, Yvon Savaria
1989	A	`conf`	A Pragmatic Approach to the Design of Self-Testing Circuits. ITC Yvon Savaria, Bruno Laguë, Bozena Kaminska
1989	A	`conf`	Design-for-Testability Using Test Design Yield and Decision Theory. ITC Bozena Kaminska, Yvon Savaria
1988	J	`jnl`	New architectures for fast convolutional encoders and threshold decoders. IEEE J. Sel. Areas Commun. David Haccoun, Pierre Lavoie, Yvon Savaria
1986	J	`jnl`	A Theory for the Design of Soft-Error-Tolerant VLSI Circuits. IEEE J. Sel. Areas Commun. Yvon Savaria, Jeremiah F. Hayes, Nicholas C. Rumin, Vinod K. Agarwal
1986	J	`jnl`	Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits. Proc. IEEE Yvon Savaria, Nicholas C. Rumin, Jeremiah F. Hayes, Vinold K. Agarwal
1984	A	`conf`	A Design for Machines with Built-In Tolerance to Soft Errors. ITC Yvon Savaria, Vinod K. Agarwal, Nicholas C. Rumin, Jeremiah F. Hayes