Yves Blaquière

59 papers C 19Misc 1Journal 19Unranked 20

Year	Rank	Type	Title / Venue / Authors
2024	C	`conf`	A Precise and Reliable Engine Knock Detection Utilizing Meta Classifier. ISCAS Amirhossein Moshrefi, Yves Blaquière, Frederic Nabki
2024	C	`conf`	Configurable and Intelligent Switched CMOS Current Driver Powering Arrays of Electrothermal Actuators for MEMS Switches. ISCAS Allan Riboullet, Frédéric Nabki, Yves Blaquière, Glenn E. R. Cowan
2024	J	`jnl`	Hybrid Graph Representation and Learning Framework for High-Level Synthesis Design Space Exploration. IEEE Access Pouya Taghipour, Eric Granger, Yves Blaquière
2023	J	`jnl`	An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform. IEEE Trans. Circuits Syst. II Express Briefs Hachem Bensalem, Yves Blaquière, Yvon Savaria
2023	—	`conf`	Toward 2.5D Structures for Multi-Channel MEMS Acoustic-Based Digital Isolators using Through Silicon Openings. NEWCAS Hamid Sadrimanesh, Yves Blaquière, Frederic Nabki
2023	—	`conf`	Toward a Polysilicon-Based Electrostatically Actuated DC MEMS Switch. NEWCAS Abdurrashid Hassan Shuaibu, Yves Blaquière, Frédéric Nabki
2022	—	`conf`	A 3.3 V 0.1-1 A Hybrid Buck-Boost Converter with 85-97 % Power Efficiency Range Highly-Suited for Battery-Powered Devices using Low-Profile High-DCR Inductor. NEWCAS Van Ha Nguyen, Xuan-Dien Do, Yves Blaquière, Glenn E. R. Cowan
2022	—	`conf`	A MEMS Electrothermal Actuator Designed for a DC Switch Aimed at Power Switching Applications and High Voltage Resilience. NEWCAS Abdurrashid Hassan Shuaibu, Frédéric Nabki, Yves Blaquière
2022	—	`conf`	A Reconfigurable Power System-in-Package Module using GaN HEMTs and IC Bare Dies on LTCC Substrate: Design - Implementation - Experiment and Future Directions. NEWCAS Van Ha Nguyen, Nueraimaiti Aimaier, Gabriel Nobert, Tan Pham, Nicolas G. Constantin, Yves Blaquière, Glenn E. R. Cowan
2022	—	`conf`	Multi-Phase Hybrid Boost Converter with High Conduction Loss Reduction and Fast Dynamic Response for Automotive Applications. NEWCAS Van Ha Nguyen, Xuan-Dien Do, Yves Blaquière, Glenn E. R. Cowan
2021	C	`conf`	A Novel Minimum-Phase Dual-Inductor Hybrid Boost Converter with PWM Voltage-Mode Controller. ISCAS Van Ha Nguyen, Abdul Hafiz Alameh, Nam Ly, Yves Blaquière, Glenn E. R. Cowan
2021	J	`jnl`	A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers. IEEE Trans. Circuits Syst. II Express Briefs Van Ha Nguyen, Nam Ly, Abdul Hafiz Alameh, Yves Blaquière, Glenn E. R. Cowan
2021	C	`conf`	Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL. ISCAS Hachem Bensalem, Yves Blaquière, Yvon Savaria
2021	C	`conf`	Compact and Low-Power Under-Voltage Lockout and Thermal-Shutdown Protection Circuits Using a Novel Low-Iq All-in-One Bandgap Comparator. ISCAS Van Ha Nguyen, Nam Ly, Abdul Hafiz Alameh, Yves Blaquière, Glenn E. R. Cowan
2021	J	`jnl`	Ring-Oscillator-Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. IEEE Trans. Instrum. Meas. Safa Berrima, Yves Blaquière, Yvon Savaria
2021	C	`conf`	SHEPWM Class-D Amplifier with a Reconfigurable Gate Driver Integrated Circuit. ISCAS Nueraimaiti Aimaier, Nam Ly, Gabriel Nobert, Yves Blaquière, Nicolas G. Constantin, Glenn E. R. Cowan
2021	C	`conf`	Towards an LTCC SiP for Control System in Safety-Critical Applications. ISCAS Gabriel Nobert, Abdul Hafiz Alameh, Nam Ly, Nicolas G. Constantin, Yves Blaquière
2020	—	`conf`	A High Voltage Multi-Purpose On-the-fly Reconfigurable Half-Bridge Gate Driver for GaN HEMTs in 0.18-μm HV SOI CMOS Technology. NEWCAS Nam Ly, Nueraimaiti Aimaier, Abdul Hafiz Alameh, Yves Blaquière, Glenn E. R. Cowan, Nicolas G. Constantin
2020	J	`jnl`	Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. IET Circuits Devices Syst. Safa Berrima, Yves Blaquière, Yvon Savaria
2020	J	`jnl`	In-FPGA Instrumentation Framework for OpenCL-Based Designs. IEEE Access Hachem Bensalem, Yves Blaquière, Yvon Savaria
2019	J	`jnl`	A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. IEEE Trans. Very Large Scale Integr. Syst. Nicolas Laflamme-Mayer, Gilbert Kowarzyk, Yves Blaquière, Yvon Savaria, Mohamad Sawan
2019	C	`conf`	Toward In-System Monitoring of OpenCL-Based Designs on FPGA. ISCAS Hachem Bensalem, Yves Blaquière, Yvon Savaria
2018	J	`jnl`	A pattern-based routing algorithm for a novel electronic system prototyping platform. Integr. Etienne Lepercq, Yves Blaquière, Yvon Savaria
2018	J	`jnl`	Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA. CoRR Mostafa Darvishi, Yves Audet, Yves Blaquière
2018	J	`jnl`	Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. Integr. Safa Berrima, Yves Blaquière, Yvon Savaria
2017	C	`conf`	A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array. ISCAS Safa Berrima, Yves Blaquière, Yvon Savaria
2017	—	`conf`	Sub-ps resolution programmable delays implemented in a Xilinx FPGA. MWSCAS Safa Berrima, Yves Blaquière, Yvon Savaria
2016	C	`conf`	A compact spatially configurable differential input stage for a field programmable interconnection network. ISCAS Wasim Hussain, Yvon Savaria, Yves Blaquière
2016	J	`jnl`	A novel spatially configurable differential interface for an electronic system prototyping platform. Integr. Wasim Hussain, Olivier Valorge, Yves Blaquière, Yvon Savaria
2016	J	`jnl`	An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform. IEEE Trans. Circuits Syst. I Regul. Pap. Wasim Hussain, Hussein Fakhoury, Patricia Desgreys, Yves Blaquière, Yvon Savaria
2016	J	`jnl`	Towards an efficient SEU effects emulation on SRAM-based FPGAs. Microelectron. Reliab. Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
2015	J	`jnl`	An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Wasim Hussain, Yves Blaquière, Yvon Savaria
2015	—	`conf`	An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs. EWDTS Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
2015	J	`jnl`	Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation. CoRR Mostafa Darvishi, Yves Audet, Yves Blaquière, Claude Thibeault
2015	C	`conf`	Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit. IOLTS Gontran Sion, Yves Blaquière, Yvon Savaria
2015	C	`conf`	Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis. IOLTS Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco
2014	J	`jnl`	A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Nicolas Laflamme-Mayer, Yves Blaquière, Yvon Savaria, Mohamad Sawan
2014	C	`conf`	Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain. ISCAS Yves Blaquière, Yan Basile-Bellavance, Safa Berrima, Yvon Savaria
2013	—	`conf`	A configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems. LASCAS Nicolas Laflamme-Mayer, Mohamad Sawan, Yves Blaquière
2013	—	`conf`	A netlist pruning tool for an electronic system prototyping platform. NEWCAS Karim Baratli, Ahmed Lakhssassi, Yves Blaquière, Yvon Savaria
2013	C	`conf`	An interface for the I ISCAS Wasim Hussain, Yvon Savaria, Yves Blaquière
2013	J	`jnl`	Configurable Input-Output Power Pad for Wafer-Scale Microelectronic Systems. IEEE Trans. Very Large Scale Integr. Syst. Nicolas Laflamme-Mayer, Walder Andre, Olivier Valorge, Yves Blaquière, Mohamad Sawan
2013	—	`conf`	Software rendering methods to display wafer scale integrated circuit dataset. CCECE Mikael Guillemot, Yves Blaquière, Yvon Savaria
2012	C	`conf`	A new approach for pin detection for an electronic system prototyping reconfigurable platform. RSP Hai H. Nguyen, Mikael Guillemot, Yvon Savaria, Yves Blaquière
2012	C	`conf`	Propagating analog signals through a fully digital network on an electronic system prototyping platform. ISCAS Omar Al-Terkawi Hasib, Walder Andre, Yves Blaquière, Yvon Savaria
2012	—	`conf`	SoC systems thermal monitoring using embedded sensor cells unit. MWSCAS Michel Sayde, Ahmed Lakhssassi, Mohammed Bougataya, Omar Terkawi, Yves Blaquière
2011	—	`conf`	A large range and fine tuning configurable Bandgap reference dedicated to wafer-scale systems. ICECS Nicolas Laflamme-Mayer, Yves Blaquière, Mohamad Sawan
2011	C	`conf`	Machine-learning framework for automatic netlist creation. ISCAS Mohamed Badreddine, Yves Blaquière, Mounir Boukadoum
2010	—	`conf`	A spatially reconfigurable fast differential interface for a wafer scale configurable platform. ICECS Olivier Valorge, Yves Blaquière, Yvon Savaria
2010	—	`conf`	Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit. ICECS Mohammed Bougataya, Oussama Berriah, Ahmed Lakhssassi, Adel-Omar Dahmane, Yves Blaquière, Yvon Savaria, Richard Norman, Richard Prytula
2009	C	`conf`	Workflow for an Electronic Configurable Prototyping System. ISCAS Etienne Lepercq, Yves Blaquière, Richard Norman, Yvon Savaria
2008	—	`conf`	Digital signal propagation on a wafer-scale smart active programmable interconnect. ICECS Olivier Valorge, Anh Tuan Nguyen, Yves Blaquière, Richard Norman, Yvon Savaria
2008	—	`conf`	Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL. ICECS Yan Basile-Bellavance, Etienne Lepercq, Yves Blaquière, Yvon Savaria
2007	—	`conf`	Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os. ICECS Yves Blaquière, Yvon Savaria, Jaouad El Fouladi
2000	C	`conf`	Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm. ISCAS Marc-André Cantin, Yves Blaquière, Yvon Savaria, Pierre Lavoie, Eric Granger
1998	Misc	`conf`	A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing. FCCM Pascal Poiré, Marc-André Cantin, Hervé Daniel, Yves Blaquière, Yvon Savaria
1996	J	`jnl`	Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yves Blaquière, Michel R. Dagenais, Yvon Savaria
1995	—	`conf`	Cost analysis of a new algorithmic-based soft-error tolerant architecture. DFT Yves Blaquière, Gabriel Gagné, Yvon Savaria, Claude Évéquoz
1990	J	`jnl`	VHDL design of a priority interrupt controller and synchronizer for the MC68008. Microprocess. Microsystems Yves Blaquière, Jacob Davidson