Yves Berviller

20 papers A 1B 3C 1Journal 7Unranked 8
YearRankTypeTitle / Venue / Authors
2023 J jnl
Road User Position and Speed Estimation via Deep Learning from Calibrated Fisheye Videos.
Sensors
Yves Berviller, Masoomeh Shireen Ansarnia, Etienne Tisserand, Patrick Schweitzer, Alain Trémeau
2022 J jnl
Contextual Detection of Pedestrians and Vehicles in Orthophotography by Fusion of Deep Learning Algorithms.
Sensors
Masoomeh Shireen Ansarnia, Etienne Tisserand, Patrick Schweitzer, Mohamed Amine Zidane, Yves Berviller
2013 — conf
Modeling and FPGA implementation of reconfigurable transcoder for real time video adaptation.
ICECS
Eric Dabellani, Hassan Rabah, Nicolas Marques, Yves Berviller, Slavisa Jovanovic, Serge Weber
2012 J jnl
Medical image denoising on field programmable gate array using finite Radon transform.
IET Signal Process.
Afandi Ahmad, Abbes Amira, Hassan Rabah, Yves Berviller
2011 — conf
An efficient VLSI implementation of H.264/AVC intra-frame transcoder.
ICECS
Michael Guarisco, Eric Dabellani, Nicolas Marques, Hassan Rabah, Yves Berviller, Serge Weber
2010 B conf
Efficient implementation of a 3-D medical imaging compression system using CAVLC.
ICIP
Afandi Ahmad, Abbes Amira, Michael Guarisco, Hassan Rabah, Yves Berviller
2010 — conf
FPGA-based architectures of finite radon transform for medical image de-noising.
APCCAS
Afandi Ahmad, Abbes Amira, Hassan Rabah, Yves Berviller
2009 J jnl
An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis.
IEEE Trans. Circuits Syst. Video Technol.
Camel Tanougast, Michael Janiaut, Yves Berviller, Hassan Rabah, Serge Weber, Ahmed Bouridane
2009 — conf
FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding.
SoCC
Michael Guarisco, Hassan Rabah, Yves Berviller, Serge Weber, Said Belkouch
2007 — conf
A Design Methodology for Power Electronics Digital Control based on an FPGA in the Loop Prototyping.
ICECS
Shahram Karimi, Philippe Poure, Yves Berviller, Shahrokh Saadate
2007 J jnl
The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation.
J. Univers. Comput. Sci.
Oscar Pérez, Yves Berviller, Camel Tanougast, Serge Weber
2005 B conf
Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis.
FPL
Michael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge Weber
2004 B conf
FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T.
FPL
Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber
2004 — conf
FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-T.
ESA/VLSI
Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber
2004 C conf
SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation.
IEEE International Workshop on Rapid System Prototyping
Camel Tanougast, Yves Berviller, Christian Mannino, Hassan Rabah, Michael Janiaut, Serge Weber
2003 J jnl
A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems.
EURASIP J. Adv. Signal Process.
Camel Tanougast, Yves Berviller, Serge Weber, Philippe Brunet
2003 A conf
Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design.
IPDPS
Camel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber
2003 — conf
Hardware Partitioning Software for Dynamically Reconfigurable SoC Design.
IWSOC
Philippe Brunet, Camel Tanougast, Yves Berviller, Serge Weber
2003 J jnl
Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system.
Microprocess. Microsystems
Camel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber, Hassan Rabah
2000 — conf
Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation.
IPDPS Workshops
Camel Tanougast, Yves Berviller, Serge Weber