Yves Bertrand - RankMe

90 papers A 10C 4Misc 13Journal 26Unranked 37

Year	Rank	Type	Title / Venue / Authors
2012	J	`jnl`	"Capacitive Sensor" to Measure Flow Electrification and Prevent Electrostatic Hazards. Sensors Thierry Paillat, Gérard Touchard, Yves Bertrand
2009	C	`conf`	An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. DDECS Florence Azaïs, Yves Bertrand, Michel Renovell
2009	J	`jnl`	Consistency constraints and 3D building reconstruction. Comput. Aided Des. Sébastien Horna, Daniel Méneveaux, Guillaume Damiand, Yves Bertrand
2009	J	`jnl`	Remote Labs for Industrial IC Testing. IEEE Trans. Learn. Technol. Beatrice Pradarelli, Laurent Latorre, Marie-Lise Flottes, Yves Bertrand, Pascal Nouet
2008	—	`conf`	Considerations on Improving the Design of CUFF Electrode for ENG Recording - Geometrical Approach, Dedicated IC, Sensitivity, Noise Rejection. BIODEVICES (2) Fabien Soulier, Lionel Gouyet, Guy Cathébras, Serge Bernard, David Guiraud, Yves Bertrand
2008	—	`conf`	Multipolar Electrode and Preamplifier Design for ENG-Signal Acquisition. BIOSTEC (Selected Papers) Fabien Soulier, Lionel Gouyet, Guy Cathébras, Serge Bernard, David Guiraud, Yves Bertrand
2008	C	`conf`	On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. IOLTS Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell
2007	—	`conf`	Building 3D indoor scenes topology from 2D architectural plans. GRAPP (GM/R) Sébastien Horna, Guillaume Damiand, Daniel Méneveaux, Yves Bertrand
2007	—	`conf`	Generic computation of bulletin boards into geometric kernels. Afrigraph Mehdi Baba-ali, David Marcheix, Xavier Skapin, Yves Bertrand
2007	—	`conf`	Low-noise ASIC and New Layout of Multipolar Electrode for both High ENG Selectivity and Parasitic Signal Rejection. ICECS Serge Bernard, Lionel Gouyet, Guy Cathébras, Fabien Soulier, David Guiraud, Yves Bertrand
2005	J	`jnl`	Automatic Building of Structured Geological Models. J. Comput. Inf. Sci. Eng. Sylvain Brandel, Sébastien Schneider, Michel Perrin, Nicolas Guiard, Jean-François Rainaud, Pascal Lienhardt, Yves Bertrand
2005	J	`jnl`	Connectivity compression in an arbitrary dimension. Vis. Comput. Sylvain Prat, Patrick Gioia, Yves Bertrand, Daniel Méneveaux
2005	J	`jnl`	Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand
2005	J	`jnl`	Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. J. Electron. Test. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
2005	—	`conf`	Test Engineering Education in Europe - The CRTC experience through the EuNICE-Test project. EDUTECH Laurent Latorre, Yves Bertrand, Michel Robert, Marie-Lise Flottes
2004	—	`conf`	Automatic building of structured geological models. Symposium on Solid Modeling and Applications Sylvain Brandel, Sébastien Schneider, Michel Perrin, Nicolas Guiard, Jean-François Rainaud, Pascal Lienhardt, Yves Bertrand
2004	J	`jnl`	Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. J. Electron. Test. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
2004	—	`conf`	Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. DELTA Marie-Lise Flottes, Yves Bertrand, Luz Balado, Emili Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich
2004	J	`jnl`	Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. J. Electron. Test. Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell
2004	—	`conf`	New implantable stimulator for the FES of paralyzed muscles. ESSCIRC Jean-Denis Techer, Serge Bernard, Yves Bertrand, Guy Cathébras, David Guiraud
2004	J	`jnl`	Topological model for two-dimensional image representation: definition and optimal extraction algorithm. Comput. Vis. Image Underst. Guillaume Damiand, Yves Bertrand, Christophe Fiorio
2003	A	`conf`	A New Methodology For ADC Test Flow Optimization. ITC Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell
2003	J	`jnl`	A-to-D converters static error detection from dynamic parameter measurement. Microelectron. J. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
2003	J	`jnl`	An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. IEEE Des. Test Comput. Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei
2003	—	`conf`	Delay Testing of MOS Transistor with Gate Oxide Short. Asian Test Symposium Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
2003	J	`jnl`	Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. J. Electron. Test. Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
2003	J	`jnl`	On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. J. Electron. Test. Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
2003	—	`conf`	Test Engineering Education in Europe: the EuNICE-Test Project. MSE Yves Bertrand, Marie-Lise Flottes, Luz Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich, Jean-Pierre Van der Heyden
2002	—	`conf`	A high accuracy triangle-wave signal generator for on-chip ADC testing. ETW Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
2002	—	`conf`	Estimating Static Parameters of A-to-D Converters from Spectral Analysis. LATW Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell, Marcelo Lubaszewski
2002	—	`conf`	European Network for Test Education. DELTA Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, Regis Lorival
2002	Misc	`conf`	Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems. VTS Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet
2002	J	`jnl`	Improving Defect Detection in Static-Voltage Testing. IEEE Des. Test Comput. Michel Renovell, Florence Azaïs, Yves Bertrand
2002	—	`conf`	Modeling gate oxide short defects in CMOS minimum transistors. ETW Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
2002	A	`conf`	On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems. DATE Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet
2002	J	`jnl`	Spécifications formelles du chanfreinage. Tech. Sci. Informatiques Franck Ledoux, Jean-Marc Mota, Agnès Arnould, Catherine Dubois, Pascale Le Gall, Yves Bertrand
2002	—	`conf`	Testing Resonant Micro-Electro-Mechanical Sensors using the Oscillation-based Test Methodology. LATW Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet
2001	Misc	`conf`	A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. VTS Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell
2001	J	`jnl`	A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs. J. Electron. Test. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
2001	—	`conf`	Analog BIST Generator for ADC Testing. DFT Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
2001	A	`conf`	Boolean and current detection of MOS transistor with gate oxide short. ITC Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand
2001	—	`conf`	Electrical Analysis of Gate Oxide Short in MOS Technologies. LATW Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
2001	—	`conf`	Geometric Modelling with CASL. WADT Franck Ledoux, Agnès Arnould, Pascale Le Gall, Yves Bertrand
2001	A	`conf`	Implementation of a linear histogram BIST for ADCs. DATE Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
2001	Misc	`conf`	N-Dimensional Gregory-Bezier for N-Dimensional Cellular Complexes. WSCG (Short Papers) Sylvain Thery, Dominique Bechmann, Yves Bertrand
2001	C	`conf`	Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing. VLSI-SOC Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet
2001	J	`jnl`	On the detectability of CMOS floating gate transistor faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand
2001	—	`conf`	On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area. LATW Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell
2001	C	`conf`	On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. VLSI-SOC Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
2001	J	`jnl`	Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST. J. Electron. Test. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
2001	J	`jnl`	Test and Testability of a Monolithic MEMS for Magnetic Field Sensing. J. Electron. Test. Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet
2000	J	`jnl`	Combining Functional and Structural Approaches for Switched-Current Circuit Testing. J. Electron. Test. Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand
2000	Misc	`conf`	Hardware Resource Minimization for Histogram-Based ADC BIST. VTS Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand
2000	—	`conf`	Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters. LATW Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
2000	—	`conf`	On the Temperature Dependencies of Analog BIST. LATW Luigi Carro, Michel Renovell, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs
2000	A	`conf`	Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. DATE Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski
2000	—	`conf`	TI-BIST: a temperature independent analog BIST for switched-capacitor filters. Asian Test Symposium Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell
2000	J	`jnl`	Thickening: an operation for animation. Comput. Animat. Virtual Worlds Sylvain Brandel, Dominique Bechmann, Yves Bertrand
2000	J	`jnl`	Topological 3D-manifolds: a statistical study of the cells. Theor. Comput. Sci. Jean Françon, Yves Bertrand
2000	—	`conf`	Topological Encoding of 3D Segmented Images. DGCI Yves Bertrand, Guillaume Damiand, Christophe Fiorio
1999	—	`conf`	A Successful Distance-Learning Experience for IC Test Education. MSE Yves Bertrand, Florence Azaïs, Marie-Lise Flottes, Regis Lorival
1999	—	`conf`	Border Map: A Topological Representation for nD Image Analysis. DGCI Yves Bertrand, Christophe Fiorio, Yann Pennaneach
1999	A	`conf`	Design, Characterization & Modelling of a CMOS Magnetic Field Sensor. DATE Laurent Latorre, Yves Bertrand, P. Hazard, Francis Pressecq, Pascal Nouet
1999	J	`jnl`	Detection of Defects Using Fault Model Oriented Test Sequences. J. Electron. Test. Michel Renovell, Florence Azaïs, Yves Bertrand
1999	—	`conf`	Functional and structural testing of switched-current circuits. ETW Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand
1999	A	`conf`	Optimal conditions for Boolean and current detection of floating gate faults. ITC Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq
1998	—	`conf`	A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing. SBCCI Marcelo Lubaszewski, Michel Renovell, Salvador Mir, Florence Azaïs, Yves Bertrand
1998	—	`conf`	A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. Asian Test Symposium Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand
1998	—	`conf`	BISTing Switched-Current Circuits. Asian Test Symposium Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand
1998	Misc	`conf`	Design-For-Testability for Switched-Current Circuits. VTS Florence Azaïs, Michel Renovell, Yves Bertrand, J.-C. Bodin
1998	A	`conf`	Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. DATE Michel Renovell, Florence Azaïs, Yves Bertrand
1998	—	`conf`	STIGMA: a 4-dimensional modeller for animation. Computer Animation and Simulation Sylvain Brandel, Dominique Bechmann, Yves Bertrand
1997	J	`jnl`	Continuous free form deformation. Comput. Networks ISDN Syst. Dominique Bechmann, Yves Bertrand, Sylvain Thery
1997	—	`conf`	MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits. ED&TC A. Dargelas, C. Gauthron, Yves Bertrand
1997	—	`conf`	On-chip analog output response compaction. ED&TC Michel Renovell, Florence Azaïs, Yves Bertrand
1997	A	`conf`	Test Strategy Sensitivity to Defect Parameters. ITC Michel Renovell, Yves Bertrand
1996	Misc	`conf`	Bridging fault coverage improvement by power supply control. VTS Michel Renovell, P. Huc, Yves Bertrand
1996	Misc	`conf`	The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault. EDCC Michel Renovell, P. Huc, Yves Bertrand
1996	Misc	`conf`	The multi-configuration: A DFT technique for analog circuits. VTS Michel Renovell, Florence Azaïs, Yves Bertrand
1995	—	`conf`	A design-for-test technique for multistage analog circuits. Asian Test Symposium Michel Renovell, Florence Azaïs, Yves Bertrand
1995	—	`conf`	Serial transistor network modeling for bridging fault simulation. Asian Test Symposium Michel Renovell, P. Huc, Yves Bertrand
1995	—	`conf`	Test configurations to enhance the testability of sequential circuits. Asian Test Symposium S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault
1995	Misc	`conf`	The concept of resistance interval: a new parametric model for realistic resistive bridging fault. VTS Michel Renovell, P. Huc, Yves Bertrand
1994	J	`jnl`	Algebraic Specification of a 3D-Modeler Based on Hypermaps. CVGIP Graph. Model. Image Process. Yves Bertrand, Jean-François Dufourd
1994	Misc	`conf`	CMOS bridging fault modeling. VTS Michel Renovell, P. Huc, Yves Bertrand
1994	Misc	`conf`	The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. EDCC Michel Renovell, P. Huc, Yves Bertrand
1993	Misc	`conf`	A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. VLSI Design Yves Bertrand, Frédéric Bancel, Michel Renovell
1993	—	`conf`	Algebraic Specification and Development in Geometric Modeling. TAPSOFT Yves Bertrand, Jean-François Dufourd, Jean Françon, Pascal Lienhardt
1993	A	`conf`	Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. ITC Yves Bertrand, Frédéric Bancel, Michel Renovell
1992	Misc	`conf`	A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs. VLSI Design Michel Renovell, M. Ildevert, Yves Bertrand