Yvain Thonnart

62 papers A* 1A 8C 6Journal 16Unranked 31

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A 3.19pJ/b Electro-Optical Router with 18ns Setup Frame-Level Routing and 1-to-6 Wavelength-Flexible Link Capacity for Photonic Interposers. ISSCC Yvain Thonnart, Christian Bernard, Stéphane Bernabé, Myriam Assous, Laura Boutafa, Benoît Charbonnier, Rémi Franiatte, César Fuguet, Olivier Guille, Vincent Josselin, Stephane Malhouitre, Laurent Mendizabal, Andre Myko, Damien Saint-Patrice, Remi Velard, Jean Charbonnier
2025	—	`conf`	13.5 An 18.5µW/qubit Cryo-CMOS Charge-Readout IC Demonstrating QAM Multiplexing for Spin Qubits. ISSCC Quentin Schmidt, Baptiste Jadot, Brian Martinez, Antoine Faurie, Tristan Meunier, Jean-Baptiste Casanova, Xavier Jehl, Yvain Thonnart, Franck Badets
2025	C	`conf`	Cryogenic Circuit Performance Prediction Using Design-Oriented Model (SEKV) On 22nm FDSOI. ISCAS Brian Martinez, Hung-Chi Han, Flávio Enrico Bergamaschi, Quentin Schmidt, Antoine Faurie, Edoardo Charbon, Yvain Thonnart, Baptiste Jadot, Xavier Jehl, Mikaël Cassé, Christian C. Enz, Franck Badets
2024	—	`conf`	A 7.4μW and 860μm CICC Quentin Schmidt, Brian Martinez, Thomas Houriez, Baptiste Jadot, Aloysius G. M. Jansen, Xavier Jehl, Tristan Meunier, Gaël Pillonnet, Gérard Billiot, Adrien Morel, Yvain Thonnart, Franck Badets
2024	J	`jnl`	Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro. IEEE J. Solid State Circuits Bastien Giraud, Sebastien Ricavy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Olivier Guille, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noel, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas
2023	—	`conf`	A Cryogenic Active Router for Qubit Array Biasing from DC to 320 MHz at 100 nm Gate Pitch. ESSCIRC Baptiste Jadot, Marcos Zurita, Gérard Billiot, Yvain Thonnart, Loïck Le Guevel, Mathieu Darnas, Candice Thomas, Jean Charbonnier, Tristan Meunier, Maud Vinet, Franck Badets, Gaël Pillonnet
2023	—	`conf`	Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro. IMW Bastien Giraud, Sebastien Ricavy, Yasser Moursy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Manuel Pezzin, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noël, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas
2023	J	`jnl`	SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration. CoRR Ivan Miro-Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Guillaume Waltener, Emmanuel Pluchart, Jean-Philippe Noel, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Yvain Thonnart, Alexandre Valentian, Frédéric Heitzmann, Fabien Clermidy
2023	J	`jnl`	SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration. IEEE J. Solid State Circuits Ivan Miro-Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Guillaume Waltener, Emmanuel Pluchart, Jean-Philippe Noel, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Yvain Thonnart, Alexandre Valentian, Frédéric Heitzmann, Fabien Clermidy
2022	J	`jnl`	Architecting Optically Controlled Phase Change Memory. ACM Trans. Archit. Code Optim. Aditya Narayan, Yvain Thonnart, Pascal Vivet, Ayse K. Coskun, Ajay Joshi
2021	J	`jnl`	Architecting Optically-Controlled Phase Change Memory. CoRR Aditya Narayan, Yvain Thonnart, Pascal Vivet, Ayse K. Coskun, Ajay Joshi
2021	—	`conf`	Designing a Multi-Chiplet Manycore System using the POPSTAR Optical NoC Architecture (Invited). SLIP Yvain Thonnart
2021	J	`jnl`	IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
2021	J	`jnl`	PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aditya Narayan, Yvain Thonnart, Pascal Vivet, Ayse K. Coskun
2021	—	`conf`	SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration. ISSCC Alicia Klinefelter, Huichu Liu, Luca Benini, Yvain Thonnart, Keith A. Bowman, Kathy Wilcox, David Bol, Alvin Loke, Ofer Shacham
2020	—	`conf`	19.2 A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot. ISSCC Loïck Le Guevel, Gérard Billiot, Xavier Jehl, Silvano De Franceschi, Marcos Zurita, Yvain Thonnart, Maud Vinet, Marc Sanquer, Romain Maurand, Aloysius G. M. Jansen, Gaël Pillonnet
2020	—	`conf`	2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm ISSCC Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
2020	A	`conf`	POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems. DATE Yvain Thonnart, Stéphane Bernabé, Jean Charbonnier, Christian Bernard, David Coriat, César Fuguet Tortolero, Pierre Tissier, Benoît Charbonnier, Stéphane Malhouitre, Damien Saint-Patrice, Myriam Assous, Aditya Narayan, Ayse K. Coskun, Denis Dutoit, Pascal Vivet
2020	A	`conf`	System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications. DATE Aditya Narayan, Yvain Thonnart, Pascal Vivet, Ajay Joshi, Ayse K. Coskun
2019	—	`conf`	Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone. ASYNC Yvain Thonnart, Pascal Vivet, Shikhanshu Agarwal, Ramesh Chauhan
2019	A	`conf`	WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs. DATE Aditya Narayan, Yvain Thonnart, Pascal Vivet, César Fuguet Tortolero, Ayse K. Coskun
2018	—	`conf`	A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm ISSCC Yvain Thonnart, Mounir Zid, Jose-Luis Gonzalez Jimenez, Guillaume Waltener, Robert Polster, Olivier Dubray, Florent Lepin, Stéphane Bernabé, Sylvie Menezo, Gabriel Pares, Olivier Castany, Laura Boutafa, Philippe Grosse, Benoît Charbonnier, Charles Baudot
2017	J	`jnl`	A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. IEEE J. Solid State Circuits Pascal Vivet, Yvain Thonnart, Romain Lemaire, Cristiano Santos, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Denis Dutoit, Fabien Clermidy, Séverine Cheramy, Abbas Sheibanyrad, Frédéric Pétrot, Eric Flamand, Jean Michailos, Alexandre Arriordaz, Lee Wang, Juergen Schloeffel
2017	C	`conf`	In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. IOLTS Ivan Miro Panades, Edith Beigné, Olivier Billoint, Yvain Thonnart
2016	—	`conf`	10 Gbps, 560 fJ/b TIA and modulator driver for optical networks-on-chip in CMOS 65nm. NEWCAS Jose-Luis Gonzalez Jimenez, Robert Polster, Guillaume Waltener, Yvain Thonnart, Eric Cassan
2016	—	`conf`	8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. ISSCC Pascal Vivet, Yvain Thonnart, Romain Lemaire, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Cristiano Santos, Fabien Clermidy, Séverine Cheramy, Frédéric Pétrot, Eric Flamand, Jean Michailos
2016	J	`jnl`	Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks. IEEE Trans. Very Large Scale Integr. Syst. Luan H. K. Duong, Zhehui Wang, Mahdi Nikdast, Jiang Xu, Peng Yang, Zhifei Wang, Zhe Wang, Rafael K. V. Maeda, Haoran Li, Xuan Wang, Sébastien Le Beux, Yvain Thonnart
2016	J	`jnl`	Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes. IEEE Trans. Very Large Scale Integr. Syst. Robert Polster, Yvain Thonnart, Guillaume Waltener, Jose-Luis Gonzalez Jimenez, Eric Cassan
2015	—	`conf`	3D advanced integration technology for heterogeneous systems. 3DIC Pascal Vivet, Christian Bernard, Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Gaël Pillonnet, Yvain Thonnart, Arnaud Garnier, Didier Lattard, Amandine Jouve, Franck Bana, Thierry Mourier, Séverine Cheramy
2015	J	`jnl`	A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart
2015	A	`conf`	Coherent crosstalk noise analyses in ring-based optical interconnects. DATE Luan H. K. Duong, Mahdi Nikdast, Jiang Xu, Zhehui Wang, Yvain Thonnart, Sébastien Le Beux, Peng Yang, Xiaowen Wu, Zhifei Wang
2015	A*	`conf`	Complementary communication path for energy efficient on-chip optical interconnects. DAC Hui Li, Sébastien Le Beux, Yvain Thonnart, Ian O'Connor
2015	C	`conf`	Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. ISCAS Edith Beigné, Fabien Clermidy, Didier Lattard, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet
2015	—	`conf`	Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects. ISVLSI Pascal Vivet, Christian Bernard, Eric Guthmuller, Ivan Miro Panades, Yvain Thonnart, Fabien Clermidy
2015	—	`conf`	Two-phase protocol converters for 3D asynchronous 1-of-n data links. ASP-DAC Julian J. H. Pontes, Pascal Vivet, Yvain Thonnart
2014	—	`conf`	27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack
2014	J	`jnl`	A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. IEEE J. Solid State Circuits Ivan Miro Panades, Edith Beigné, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Farhat Thabet, Benoît Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, Didier Fuin
2014	—	`conf`	Introduction to the special session on "Silicon photonic interconnects: an illusion or a realistic solution?". NOCS Jiang Xu, Sébastien Le Beux, Yvain Thonnart
2014	—	`conf`	Technology assessment of silicon interposers for manycore SoCs: Active, passive, or optical? NOCS Yvain Thonnart, Mounir Zid
2013	—	`conf`	A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. ESSCIRC Edith Beigné, Ivan Miro-Panades, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Farhat Thabet, Benoît Tain, K. Benchehida, Sylvain Engels, Robin Wilson, Didier Fuin
2013	J	`jnl`	An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip. IEEE Trans. Computers Sahar Foroutan, Yvain Thonnart, Frédéric Pétrot
2013	C	`conf`	Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. VLSI-SoC Bertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart, Jean-Philippe Noel, Philippe Flatresse, Edith Beigné
2013	A	`conf`	Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson
2012	—	`conf`	A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits. ASYNC Yvain Thonnart, Edith Beigné, Pascal Vivet
2011	C	`conf`	3D NoC using through silicon Via: An asynchronous implementation. VLSI-SoC Pascal Vivet, Denis Dutoit, Yvain Thonnart, Fabien Clermidy
2010	—	`conf`	A 477mW NoC-based digital baseband for MIMO 4G SDR. ISSCC Fabien Clermidy, Christian Bernard, Romain Lemaire, Jérôme Martin, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet, Norbert Wehn
2010	—	`conf`	A Markov chain based method for NoC end-to-end latency evaluation. IPDPS Workshops Sahar Foroutan, Yvain Thonnart, Richard Hersemeule, Ahmed Jerraya
2010	A	`conf`	A fully-asynchronous low-power framework for GALS NoC integration. DATE Yvain Thonnart, Pascal Vivet, Fabien Clermidy
2010	A	`conf`	An analytical method for evaluating Network-on-Chip performance. DATE Sahar Foroutan, Yvain Thonnart, Richard Hersemeule, Ahmed Jerraya
2010	—	`conf`	Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms. NOCS Yvain Thonnart, Romain Lemaire, Fabien Clermidy
2009	—	`conf`	A Communication and configuration controller for NoC based reconfigurable data flow architecture. NOCS Fabien Clermidy, Romain Lemaire, Yvain Thonnart, Pascal Vivet
2009	J	`jnl`	An Asynchronous Power Aware and Adaptive NoC Based Circuit. IEEE J. Solid State Circuits Edith Beigné, Fabien Clermidy, Hélène Lhermet, Sylvain Miermont, Yvain Thonnart, Xuan-Tu Tran, Alexandre Valentian, Didier Varreau, Pascal Vivet, Xavier Popon, Hugo Lebreton
2009	C	`conf`	An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application. DSD Fabien Clermidy, Romain Lemaire, Xavier Popon, Dimitri Ktenas, Yvain Thonnart
2009	—	`conf`	Design and Implementation of a GALS Adapter for ANoC Based Architectures. ASYNC Yvain Thonnart, Edith Beigné, Pascal Vivet
2009	J	`jnl`	Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application. IET Comput. Digit. Tech. Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach
2009	J	`jnl`	Power Reduction of Asynchronous Logic Circuits Using Activity Detection. IEEE Trans. Very Large Scale Integr. Syst. Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet
2008	—	`conf`	A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. NOCS Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach
2008	—	`conf`	Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction. ASYNC Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet
2008	A	`conf`	Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures. DATE Nicolas Coste, Hubert Garavel, Holger Hermanns, Richard Hersemeule, Yvain Thonnart, Meriem Zidouni
2007	—	`conf`	ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. NOCS Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet
2007	—	`conf`	Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip. ASYNC Gwen Salaün, Wendelin Serwe, Yvain Thonnart, Pascal Vivet
2007	—	`conf`	Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip. NOCS Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach