Yuzo Takamatsu

66 papers A* 1A 2C 2Misc 5Journal 24Unranked 32
YearRankTypeTitle / Venue / Authors
2009 Misc conf
A Novel Approach for Improving the Quality of Open Fault Diagnosis.
VLSI Design
Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
2009 J jnl
Addressing Defect Coverage through Generating Test Vectors for Transistor Defects.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2009 J jnl
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation.
Inf. Media Technol.
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu
2009 J jnl
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation.
IPSJ Trans. Syst. LSI Des. Methodol.
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2009 A conf
Diagnostic test generation for transition faults using a stuck-at ATPG tool.
ITC
Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu
2009 Misc conf
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.
VLSI Design
Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu
2009 — conf
New Class of Tests for Open Faults with Considering Adjacent Lines.
Asian Test Symposium
Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume
2008 J jnl
A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information.
IEICE Trans. Inf. Syst.
Koji Yamazaki, Yuzo Takamatsu
2008 J jnl
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information.
IEICE Trans. Inf. Syst.
Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki
2008 J jnl
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools.
IEICE Trans. Inf. Syst.
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2008 — conf
Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults.
ATS
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2008 J jnl
Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2008 J jnl
Post-BIST Fault Diagnosis for Multiple Faults.
IEICE Trans. Inf. Syst.
Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
2007 — conf
Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines.
ATS
Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume
2007 Misc conf
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation.
VLSI Design
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu
2007 — conf
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.
DFT
Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
2007 — conf
Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator.
ATS
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2007 — conf
Timing-Aware Diagnosis for Small Delay Defects.
DFT
Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu
2006 — conf
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits.
ASP-DAC
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2006 — conf
Diagnosis of Transistor Shorts in Logic Test Environment.
ATS
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu
2006 — conf
Effective Post-BIST Fault Diagnosis for Multiple Faults.
DFT
Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
2006 — conf
Fanout-based fault diagnosis for open faults on pass/fail information.
ATS
Koji Yamazaki, Yuzo Takamatsu
2006 J jnl
On Finding Don't Cares in Test Sequences for Sequential Circuits.
IEICE Trans. Inf. Syst.
Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu
2005 J jnl
A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu
2005 — conf
On the fault diagnosis in the presence of unknown fault models using pass/fail information.
ISCAS (3)
T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu
2005 J jnl
Test cost reduction for logic circuits: Reduction of test data volume and test application time.
Syst. Comput. Jpn.
Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu
2004 — conf
Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set.
Asian Test Symposium
Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu
2004 — conf
Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests.
Asian Test Symposium
Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu
2004 J jnl
Generation of Test Sequences with Low Power Dissipation for Sequential Circuits.
IEICE Trans. Inf. Syst.
Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu
2004 — conf
Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction.
Asian Test Symposium
Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu
2003 C conf
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits.
ICCD
Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz
2003 — conf
BIST Based Fault Diagnosis Using Ambiguous Test Set.
DFT
Hiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu
2002 — conf
A Method to Reduce Power Dissipation during Test for Sequential Circuits.
Asian Test Symposium
Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu
2002 C conf
An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets.
PRDC
Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu
2002 — conf
Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits.
DELTA
Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu
2002 J jnl
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu
2002 — conf
Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints.
Asian Test Symposium
Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu
2001 A conf
On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits.
ITC
Keith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu
2001 — conf
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits.
Asian Test Symposium
Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu
2001 — conf
Test Generation for Double Stuck-at Faults.
Asian Test Symposium
Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu
2000 J jnl
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.
J. Electron. Test.
Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
2000 — conf
Fault models and test generation for IDDQ testing: embedded tutorial.
ASP-DAC
Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
2000 Misc conf
General BIST-Amenable Method of Test Generation for Iterative Logic Arrays.
VTS
Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu
2000 J jnl
Identification of redundant faults in combinational circuits.
Syst. Comput. Jpn.
Tetsuro Minamiyama, Yuzo Takamatsu
2000 J jnl
Static test compaction for IDDQ testing of bridging faults in sequential circuits.
Syst. Comput. Jpn.
Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita
2000 — conf
Test sequence compaction for sequential circuits with reset states.
Asian Test Symposium
Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita
1999 Misc conf
A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations.
VTS
Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu
1999 — conf
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.
Asian Test Symposium
Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
1999 — conf
Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators.
Asian Test Symposium
Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Nobuhiro Yanagida
1998 — conf
Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation.
Asian Test Symposium
Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu
1998 — conf
Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths.
Asian Test Symposium
Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu
1997 — conf
A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits.
Asian Test Symposium
Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga
1997 — conf
Design of C-Testable Multipliers Based on the Modified Booth Algorithm.
Asian Test Symposium
Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu
1997 J jnl
Tests for small gate delay faults in combinational circuits and a test generation method.
Syst. Comput. Jpn.
Hiroshi Takahashi, Takashi Watanabe, Toshiyuki Matsunaga, Yuzo Takamatsu
1996 — conf
Multiple Fault Diagnosis in Sequential Circuits Using Sensitizing Sequence Pairs.
FTCS
Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu
1995 J jnl
A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects.
IEICE Trans. Inf. Syst.
Xiangqiu Yu, Hiroshi Takahashi, Yuzo Takamatsu
1995 — conf
Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing.
Asian Test Symposium
Hiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu
1995 — conf
Generation of tenacious tests for small gate delay faults in combinational circuits.
Asian Test Symposium
Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu
1995 J jnl
Multiple Fault Diagnosis by Sensitizing Input Pairs.
IEEE Des. Test Comput.
Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu
1995 J jnl
Multiple fault diagnosis in combinational circuits using sensitizing input-pairs.
Syst. Comput. Jpn.
Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu
1995 J jnl
Test generation for sequential circuits using parallel fault simulation with random inputs.
Syst. Comput. Jpn.
Yuzo Takamatsu, Isao Higashi, Tsuyoshi Kodama
1990 — conf
Exponetiation in Finite Fields Using Dual Basis Multiplier.
AAECC
Masakatu Morii, Yuzo Takamatsu
1990 J jnl
Extended selection of switching target faults in CONT algorithm for test generation.
J. Electron. Test.
Yuzo Takamatsu, Kozo Kinoshita
1989 J jnl
CONT: a concurrent test generation system.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuzo Takamatsu, Kozo Kinoshita
1988 J jnl
Test research in Japan.
IEEE Des. Test
Hideo Fujiwara, Yuzo Takamatsu, Takashi Nanya, Teruhiko Yamada, Hideo Tamamoto, Kiyoshi Furuya
1983 A* conf
Test generation for scan design circuits with tri-state modules and bidirectional terminals.
DAC
Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara