Yuzheng Ding

21 papers A* 1A 7B 1C 1Journal 9
YearRankTypeTitle / Venue / Authors
2016 — ch.
FPGA Technology Mapping.
Encyclopedia of Algorithms
Jason Cong, Yuzheng Ding
2008 — ch.
FPGA Technology Mapping.
Encyclopedia of Algorithms
Jason Cong, Yuzheng Ding
2005 A conf
The effect of post-layout pin permutation on timing.
FPGA
Yuzheng Ding, Peter Suaris, Nan-Chi Chou
2004 A conf
Incremental physical resynthesis for timing optimization.
FPGA
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou
1999 A conf
Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution.
FPGA
Jason Cong, Chang Wu, Yuzheng Ding
1996 J jnl
Combinational logic synthesis for LUT based field programmable gate arrays.
ACM Trans. Design Autom. Electr. Syst.
Jason Cong, Yuzheng Ding
1996 A conf
RASP: A General Logic Synthesis System for SRAM-Based FPGAs.
FPGA
Jason Cong, John Peck, Yuzheng Ding
1995 A conf
On Nominal Delay Minimization in LUT-based FPGA Technology Mapping.
FPGA
Jason Cong, Yuzheng Ding
1994 J jnl
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jason Cong, Yuzheng Ding
1994 J jnl
LUT-based FPGA technology mapping under arbitrary net-delay models.
Comput. Graph.
Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen
1994 J jnl
On area/depth trade-off in LUT-based FPGA technology mapping.
IEEE Trans. Very Large Scale Integr. Syst.
Jason Cong, Yuzheng Ding
1994 J jnl
On nominal delay minimization in LUT-based FPGA technology mapping.
Integr.
Jason Cong, Yuzheng Ding
1994 J jnl
On the Complexity of Building an Interval Heap.
Inf. Process. Lett.
Yuzheng Ding, Mark Allen Weiss
1993 A conf
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs.
ICCAD
Jason Cong, Yuzheng Ding
1993 A* conf
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping.
DAC
Jason Cong, Yuzheng Ding
1993 B conf
The K-D Heap: An Efficient Multi-dimensional Priority Queue.
WADS
Yuzheng Ding, Mark Allen Weiss
1993 J jnl
The Relaxed min-max Heap.
Acta Informatica
Yuzheng Ding, Mark Allen Weiss
1992 C conf
An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization.
ICCD
Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen
1992 A conf
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.
ICCAD
Jason Cong, Yuzheng Ding
1992 J jnl
Best case lower bounds for Heapsort.
Computing
Yuzheng Ding, Mark Allen Weiss
1992 J jnl
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization.
IEEE Des. Test Comput.
Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar