Yuze Chi - RankMe

51 papers A* 4A 18Misc 4Journal 22Unranked 2

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Automated Design Space Exploration in High-Level Physical Synthesis. ICCAD Linfeng Du, Jiawei Liang, Jason Lau, Yuze Chi, Yutong Xie, Chunyou Su, Afzal Ahmad, Zifan He, Jake Ke, Jinming Ge, Jason Cong, Wei Zhang, Licheng Guo
2025	Misc	`conf`	NoH: NoC Compilation in High-Level Synthesis. FCCM Huifeng Ke, Sihao Liu, Licheng Guo, Zifan He, Linghao Song, Suhail Basalama, Yuze Chi, Tony Nowatzki, Jason Cong
2024	J	`jnl`	PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. ACM Trans. Reconfigurable Technol. Syst. Moazin Khatti, Xingyu Tian, Ahmad Sedigh Baroughi, Akhil Raj Baranwal, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang
2024	A	`conf`	RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. ICCAD Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo
2024	J	`jnl`	RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. CoRR Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo
2024	—	`conf`	TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. ASPLOS (3) Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong
2023	A	`conf`	Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. FPGA Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong
2023	J	`jnl`	Democratizing Domain-Specific Computing. Commun. ACM Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
2023	Misc	`conf`	PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. FCCM Moazin Khatti, Xingyu Tian, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang
2023	J	`jnl`	RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
2023	J	`jnl`	SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs. ACM Trans. Reconfigurable Technol. Syst. Xingyu Tian, Zhifan Ye, Alec Lu, Licheng Guo, Yuze Chi, Zhenman Fang
2023	J	`jnl`	TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. CoRR Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong
2023	J	`jnl`	TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. ACM Trans. Reconfigurable Technol. Syst. Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong
2023	J	`jnl`	TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Young Kyu Choi, Yuze Chi, Jason Lau, Jason Cong
2022	A	`conf`	Accelerating SSSP for Power-Law Graphs. FPGA Yuze Chi, Licheng Guo, Jason Cong
2022	J	`jnl`	Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. CoRR Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong
2022	J	`jnl`	Democratizing Domain-Specific Computing. CoRR Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
2022	Misc	`conf`	PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators. ICASSP Linghao Song, Yuze Chi, Jason Cong
2022	A	`conf`	RapidStream: Parallel Physical Implementation of FPGA HLS Designs. FPGA Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
2022	J	`jnl`	SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs. CoRR Xingyu Tian, Zhifan Ye, Alec Lu, Licheng Guo, Yuze Chi, Zhenman Fang
2022	A	`conf`	SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation. FPGA Atefeh Sohrabizadeh, Yuze Chi, Jason Cong
2022	A*	`conf`	Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication. DAC Linghao Song, Yuze Chi, Licheng Guo, Jason Cong
2022	A	`conf`	Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. FPGA Linghao Song, Yuze Chi, Atefeh Sohrabizadeh, Young-kyu Choi, Jason Lau, Jason Cong
2022	—	`conf`	StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing. CICC Atefeh Sohrabizadeh, Yuze Chi, Jason Cong
2022	J	`jnl`	TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design. CoRR Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong
2021	A	`conf`	AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. FPGA Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong
2021	—	`—`	Design Automation and Optimization for Memory-Bound Application Accelerators. Yuze Chi
2021	Misc	`conf`	Extending High-Level Synthesis for Task-Parallel Programs. FCCM Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong
2021	A	`conf`	Extending High-Level Synthesis for Task-Parallel Programs. FPGA Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong
2021	A	`conf`	HBM Connect: High-Performance HLS Interconnect for FPGA HBM. FPGA Young-kyu Choi, Yuze Chi, Weikang Qiao, Nikola Samardzic, Jason Cong
2021	J	`jnl`	Pyxis: An Open-Source Performance Dataset of Sparse Accelerators. CoRR Linghao Song, Yuze Chi, Jason Cong
2021	J	`jnl`	SPA-GCN: Efficient and Flexible GCN Accelerator with an Application for Graph Similarity Computation. CoRR Atefeh Sohrabizadeh, Yuze Chi, Jason Cong
2021	J	`jnl`	Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication. CoRR Linghao Song, Yuze Chi, Licheng Guo, Jason Cong
2021	J	`jnl`	Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. CoRR Linghao Song, Yuze Chi, Atefeh Sohrabizadeh, Young-kyu Choi, Jason Lau, Jason Cong
2020	A*	`conf`	Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. DAC Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong
2020	A	`conf`	Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. FPGA Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong
2020	A*	`conf`	Exploiting Computation Reuse for Stencil Accelerators. DAC Yuze Chi, Jason Cong
2020	J	`jnl`	Extending High-Level Synthesis for Task-Parallel Programs. CoRR Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong
2020	J	`jnl`	FLASH: Fast, Parallel, and Accurate Simulator for HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Young-kyu Choi, Yuze Chi, Jie Wang, Jason Cong
2020	A	`conf`	HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration. FPGA Jiajie Li, Yuze Chi, Jason Cong
2020	J	`jnl`	When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization. CoRR Young-kyu Choi, Yuze Chi, Jie Wang, Licheng Guo, Jason Cong
2019	J	`jnl`	GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guohao Dai, Tianhao Huang, Yuze Chi, Jishen Zhao, Guangyu Sun, Yongpan Liu, Yu Wang, Yuan Xie, Huazhong Yang
2019	A	`conf`	HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang
2019	A	`conf`	Rapid Cycle-Accurate Simulator for High-Level Synthesis. FPGA Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang
2018	A	`conf`	An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only). FPGA Yuze Chi, Peipei Zhou, Jason Cong
2018	J	`jnl`	Rapid Cycle-Accurate Simulator for High-Level Synthesis. CoRR Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang
2018	A	`conf`	SODA: stencil with optimized dataflow architecture. ICCAD Yuze Chi, Jason Cong, Peng Wei, Peipei Zhou
2017	A	`conf`	ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture. FPGA Guohao Dai, Tianhao Huang, Yuze Chi, Ningyi Xu, Yu Wang, Huazhong Yang
2016	A	`conf`	FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search. FPGA Guohao Dai, Yuze Chi, Yu Wang, Huazhong Yang
2016	A*	`conf`	NXgraph: An efficient graph processing system on a single machine. ICDE Yuze Chi, Guohao Dai, Yu Wang, Guangyu Sun, Guoliang Li, Huazhong Yang
2015	J	`jnl`	NXgraph: An Efficient Graph Processing System on a Single Machine. CoRR Yuze Chi, Guohao Dai, Yu Wang, Guangyu Sun, Guoliang Li, Huazhong Yang