Yutaka Masuda - RankMe

33 papers A* 1A 6B 1C 3Journal 12Unranked 10

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Cross-Layer Approximate Computing and Critical Path Isolation for Energy-Efficient and Variation-Tolerant Design. MCSoC Meisei Yamaguchi, Yutaka Masuda, Tohru Ishihara
2025	J	`jnl`	Optoelectronic Pipeline Architecture of Convolutional RNN for Energy Efficient Inference at the Speed of Light. IEICE Trans. Electron. Chunlu Wang, Yutaka Masuda, Tohru Ishihara
2025	—	`conf`	Piecewise-Linear Approximation of Self-Attention and Its Accuracy-Aware Training for Area-Efficient Vision Transformer Inference Accelerator. ISQED Teppei Kawamura, Yutaka Masuda, Tohru Ishihara
2025	—	`conf`	Utilizing Wide Range Energy/Delay Tradeoffs in Logarithmic Multipliers to Reduce Energy Dissipated for AI Inference Workloads. MCSoC Tai-Feng Chen, Yutaka Masuda, Tohru Ishihara
2024	J	`jnl`	Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara
2024	J	`jnl`	Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takumi Komori, Yutaka Masuda, Tohru Ishihara
2023	—	`conf`	A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design. SOCC Tai-Feng Chen, Yutaka Masuda, Tohru Ishihara
2023	J	`jnl`	An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Lingxiao Hou, Yutaka Masuda, Tohru Ishihara
2023	A	`conf`	An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits. DATE Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara
2023	J	`jnl`	Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yutaka Masuda, Yusei Honda, Tohru Ishihara
2023	C	`conf`	Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design. IOLTS Yusei Honda, Yutaka Masuda, Tohru Ishihara
2022	J	`jnl`	Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taiyu Cheng, Yutaka Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto
2022	—	`conf`	An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers. ASP-DAC Lingxiao Hou, Yutaka Masuda, Tohru Ishihara
2022	J	`jnl`	Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
2022	B	`conf`	DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms. RTCSA Takumi Komori, Yutaka Masuda, Tohru Ishihara
2022	J	`jnl`	Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yutaka Masuda, Jun Nagayama, Taiyu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
2022	—	`conf`	Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks. ISVLSI Taisei Ichikawa, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
2022	A*	`conf`	Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. DAC Naoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
2021	A	`conf`	Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. DATE Yutaka Masuda, Jun Nagayama, Taiyu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
2021	C	`conf`	Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing. IOLTS Kazuki Yoshisue, Yutaka Masuda, Tohru Ishihara
2021	—	`conf`	Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. ISQED Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
2021	J	`jnl`	Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Naoki Hattori, Jun Shiomi, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
2020	—	`conf`	Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. ISVLSI Khyati Kiyawat, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
2019	—	`conf`	An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. PHOTONICS@SC Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi
2019	J	`jnl`	MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yutaka Masuda, Masanori Hashimoto
2018	J	`jnl`	Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving. IEEE Trans. Very Large Scale Integr. Syst. Yutaka Masuda, Takao Onoye, Masanori Hashimoto
2018	A	`conf`	Comparing voltage adaptation performance between replica and in-situ timing monitors. ICCAD Yutaka Masuda, Jun Nagayama, Hirotaka Takeno, Yoshimasa Ogawa, Yoichi Momiyama, Masanori Hashimoto
2018	—	`conf`	MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits. ASP-DAC Yutaka Masuda, Masanori Hashimoto
2017	J	`jnl`	Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yutaka Masuda, Takao Onoye, Masanori Hashimoto
2016	A	`conf`	Critical path isolation for time-to-failure extension and lower voltage operation. ICCAD Yutaka Masuda, Masanori Hashimoto, Takao Onoye
2016	C	`conf`	Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms. IOLTS Yutaka Masuda, Masanori Hashimoto, Takao Onoye
2015	A	`conf`	Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise. ICCAD Yutaka Masuda, Masanori Hashimoto, Takao Onoye
2015	A	`conf`	Stochastic timing error rate estimation under process and temporal variations. ITC Shoichi Iizuka, Yutaka Masuda, Masanori Hashimoto, Takao Onoye