Yusuke Ohtomo

26 papers Journal 14Unranked 12
YearRankTypeTitle / Venue / Authors
2015 J jnl
An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi-𝕍
IEEE Trans. Very Large Scale Integr. Syst.
Nobutaro Shibata, Yusuke Ohtomo, Mika Nishisaka, Yasuhiro Sato
2013 — conf
A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS.
ASP-DAC
Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2013 — conf
Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS.
MWSCAS
Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Hiroshi Koizumi, Mitsuo Nakamura
2013 J jnl
Small and Low-Cost Dual-Rate Optical Triplexer for OLT Transceivers in 10G/1G Co-existing 10G-EPON Systems.
IEICE Trans. Electron.
Atsushi Kanda, Akira Ohki, Takeshi Kurosaki, Hiroaki Sanjoh, Kota Asaka, Ryoko Yoshimura, Toshio Ito, Makoto Nakamura, Masafumi Nogawa, Yusuke Ohtomo, Mikio Yoneyama
2012 — conf
A 10Gb/s burst-mode laser diode driver for burst-by-burst power saving.
ISSCC
Hiroshi Koizumi, Minoru Togashi, Masafumi Nogawa, Yusuke Ohtomo
2012 — conf
A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS.
ASP-DAC
Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2012 J jnl
Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2012 — conf
Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control.
MWSCAS
Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura
2011 J jnl
An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System.
IEICE Trans. Electron.
Hiroaki Katsurai, Hideki Kamitsuna, Hiroshi Koizumi, Jun Terada, Yusuke Ohtomo, Tsugumichi Shibata
2011 — conf
Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors.
ISOCC
Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera
2010 — conf
A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS.
CICC
Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2009 — conf
Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit.
ISSCC
Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto
2008 J jnl
A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs.
IEICE Trans. Electron.
Yusuke Ohtomo, Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minoru Togashi, Kiyomi Kumozaki
2008 J jnl
A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC.
IEEE J. Solid State Circuits
Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo
2008 — conf
A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC.
ISSCC
Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo
2008 — conf
A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion.
ISSCC
Tomoaki Kawamura, Yusuke Ohtomo, Kazuyoshi Nishimura, Noboru Ishihara
2008 J jnl
A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI.
IEICE Trans. Electron.
Yusuke Ohtomo, Hiroshi Koizumi, Kazuyoshi Nishimura, Masafumi Nogawa
2008 J jnl
A wide range, over 9.6ns, skew compensation LSI for a flexible optical access system.
IEICE Electron. Express
Yoshihito Sakai, Hideaki Kimura, Yusuke Ohtomo, Makoto Tsubokawa
2007 J jnl
High sensitivity APD burst-mode receiver for 10Gbit/s TDM-PON system.
IEICE Electron. Express
Takashi Nakanishi, Ken-Ichi Suzuki, Youichi Fukada, Naoto Yoshimoto, Makoto Nakamura, Kazutoshi Kato, Kazuyoshi Nishimura, Yusuke Ohtomo, Makoto Tsubokawa
2007 — conf
SE3 Last Mile Access Options: PON/DSL/Cable/Wireless.
ISSCC
Larry DeVito, Yusuke Ohtomo
2006 — conf
A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOS.
ISSCC
Masafumi Nogawa, Yusuke Ohtomo, Shunji Kimura, Kazuyoshi Nishimura, Tomoaki Kawamura, Minoru Togashi
2006 J jnl
A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS.
IEEE J. Solid State Circuits
Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa
1999 J jnl
A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATM switch based on scalable distributed arbitration.
IEEE J. Solid State Circuits
Eiji Oki, Naoaki Yamanaka, Yusuke Ohtomo, Kazuhiko Okazaki, Ryusuke Kawano
1998 J jnl
A data-transition look-ahead DFF circuit for statistical reduction in power consumption.
IEEE J. Solid State Circuits
Masafumi Nogawa, Yusuke Ohtomo
1994 J jnl
BiCMOS circuit technology for a 704 MHz ATM switch LSI.
IEEE J. Solid State Circuits
Yusuke Ohtomo, Sadayuki Yasuda, Minoru Togashi, Massyuki Ino, Yasuyuki Tanabe, Jun-ichi Inoue, Masafumi Nogawa, Sshigeki Hino
1992 J jnl
A 250-Mb/s, 700-mW, 32-highway*8-b S/P converter LSI with cross-access memory.
IEEE J. Solid State Circuits
Yusuke Ohtomo, Masao Suzuki