Yusuke Matsunaga

63 papers A* 5A 9C 7Journal 27Unranked 15

Year	Rank	Type	Title / Venue / Authors
2019	C	`conf`	An Efficient SAT-Attack Algorithm Against Logic Encryption. IOLTS Yusuke Matsunaga, Masayoshi Yoshimura
2017	J	`jnl`	An Accelerating Technique for SAT-based ATPG. IPSJ Trans. Syst. LSI Des. Methodol. Yusuke Matsunaga
2016	J	`jnl`	A Test Pattern Compaction Method Using SAT-Based Fault Grouping. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yusuke Matsunaga
2016	J	`jnl`	Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yusuke Matsunaga
2015	—	`conf`	Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique. ASP-DAC Yusuke Matsunaga
2014	J	`jnl`	Synthesis Algorithm for Parallel Index Generator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yusuke Matsunaga
2014	A	`conf`	Synthesis algorithm of parallel index generation units. DATE Yusuke Matsunaga
2013	J	`jnl`	An Exact Approach for GPC-Based Compressor Tree Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2013	J	`jnl`	Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga
2012	J	`jnl`	A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. IPSJ Trans. Syst. LSI Des. Methodol. Taiga Takata, Yusuke Matsunaga
2012	J	`jnl`	An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. Inf. Media Technol. Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
2012	J	`jnl`	An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
2012	C	`conf`	Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	—	`conf`	A Soft Error Tolerance Estimation Method for Sequential Circuits. DFT Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
2011	C	`conf`	A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. IOLTS Taiga Takata, Yusuke Matsunaga
2011	J	`jnl`	Multi-Operand Adder Synthesis Targeting FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2011	C	`conf`	Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	A	`conf`	Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. ISLPED Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2010	A	`conf`	A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). FPGA Taiga Takata, Yusuke Matsunaga
2010	—	`conf`	Multi-operand adder synthesis on FPGAs using generalized parallel counters. ASP-DAC Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2009	—	`conf`	An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. ACM Great Lakes Symposium on VLSI Taiga Takata, Yusuke Matsunaga
2009	J	`jnl`	Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs. IPSJ Trans. Syst. LSI Des. Methodol. Taiga Takata, Yusuke Matsunaga
2009	J	`jnl`	Binding Refinement for Multiplexer Reduction. Inf. Media Technol. Sho Kodama, Yusuke Matsunaga
2009	J	`jnl`	Binding Refinement for Multiplexer Reduction. IPSJ Trans. Syst. LSI Des. Methodol. Sho Kodama, Yusuke Matsunaga
2009	J	`jnl`	Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taiga Takata, Yusuke Matsunaga
2009	J	`jnl`	Framework for Parallel Prefix Adder Synthesis Considering Switching Activities. IPSJ Trans. Syst. LSI Des. Methodol. Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2008	J	`jnl`	A Behavioral Synthesis Method with Special Functional Units. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tsuyoshi Sadakata, Yusuke Matsunaga
2008	—	`conf`	An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis. ASP-DAC Tsuyoshi Sadakata, Yusuke Matsunaga
2008	—	`conf`	Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. ASP-DAC Taiga Takata, Yusuke Matsunaga
2008	J	`jnl`	Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Makoto Sugihara, Yusuke Matsunaga, Kazuaki J. Murakami
2008	C	`conf`	Synthesis of parallel prefix adders considering switching activities. ICCD Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2007	J	`jnl`	A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tsuyoshi Sadakata, Yusuke Matsunaga
2007	—	`conf`	Area minimization algorithm for parallel prefix adders under bitwise delay constraints. ACM Great Lakes Symposium on VLSI Taeko Matsunaga, Yusuke Matsunaga
2007	J	`jnl`	Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yusuke Matsunaga
2007	J	`jnl`	Special Section on VLSI Design and CAD Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yusuke Matsunaga
2007	J	`jnl`	Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. IEICE Trans. Electron. Makoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki J. Murakami
2007	J	`jnl`	Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taeko Matsunaga, Yusuke Matsunaga
2006	C	`conf`	A character size optimization technique for throughput enhancement of character projection lithography. ISCAS Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
2006	J	`jnl`	Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Trans. Electron. Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
2006	—	`conf`	Development of practical ATPG tool with flexible interface. ATS Masayoshi Yoshimura, Yusuke Matsunaga
2005	—	`conf`	Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. SoC Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
2004	—	`conf`	Enhancing the performance of multi-cycle path analysis in an industrial setting. ASP-DAC Hiroyuki Higuchi, Yusuke Matsunaga
2004	—	`conf`	Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. ISVLSI Makoto Sugihara, Kazuaki J. Murakami, Yusuke Matsunaga
2002	J	`jnl`	An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yusuke Matsunaga
2002	—	`conf`	The statistical longest path problem and its application to delay analysis of logical circuits. Timing Issues in the Specification and Synthesis of Digital Systems Ei Ando, Masafumi Yamashita, Toshio Nakata, Yusuke Matsunaga
1998	A	`conf`	On accelerating pattern matching for technology mapping. ICCAD Yusuke Matsunaga
1996	A*	`conf`	A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines. DAC Hiroyuki Higuchi, Yusuke Matsunaga
1996	A*	`conf`	An Efficient Equivalence Checker for Combinational Circuits. DAC Yusuke Matsunaga
1995	J	`jnl`	A New Algorithm for Boolean Matching Utilizing Structural Information. IEICE Trans. Inf. Syst. Yusuke Matsunaga
1995	—	`conf`	Implicit prime compatible generation for minimizing incompletely specified finite state machines. ASP-DAC Hiroyuki Higuchi, Yusuke Matsunaga
1994	A	`conf`	LP based cell selection with constraints of timing, area, and power consumption. ICCAD Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita
1993	A*	`conf`	On Computing the Transitive Closure of a State Transition Relation. DAC Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton
1993	J	`jnl`	Variable ordering algorithms for ordered binary decision diagrams and their evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga
1991	A*	`conf`	A Resynthesis Approach for Network Optimization. DAC Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
1991	A	`conf`	Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. ICCAD Masahiro Fujita, Yusuke Matsunaga
1991	—	`conf`	On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. EURO-DAC Masahiro Fujita, Yusuke Matsunaga, Taeko Kakuda
1990	A	`conf`	Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. ICCAD Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda
1990	A*	`conf`	Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. DAC Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita
1990	C	`conf`	Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams. ICCD Hitomi Sato, Norikazu Takahashi, Yusuke Matsunaga, Masahiro Fujita
1990	A	`conf`	Multi-Level Logic Minimization Across Latch Boundaries. ICCAD Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda
1989	A	`conf`	Multi-level logic optimization using binary decision diagrams. ICCAD Yusuke Matsunaga, Masahiro Fujita
1988	—	`conf`	co-LODEX: A Cooperative Expert System for Logic design. FGCS Fumihiro Maruyama, Taeko Kakuda, Yusuke Matsunaga, Yoriko Minoda, Shuho Sawada, Nobuaki Kawato
1986	J	`jnl`	A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki