Yusuke Kanno

12 papers A* 1Journal 7Unranked 4
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 20-GHz Low-Noise RF Pulse Generator for Silicon Quantum Computer with 137.4-fs Jitter.
IEICE Trans. Electron.
Takayasu Norimatsu, Yusuke Wachi, Takuji Miki, Yusuke Kanno, Ryozo Takahashi, Takashi Ogawa, Takeru Utsugi, Tomonori Sekiguchi, Makoto Nagata, Hiroyuki Mizuno
2024 — conf
A cryogenic pulse shaper for spin qubit control utilizing 1ns-time-resolution ADCs on an active silicon interposer operating at sub-100 mK temperatures.
A-SSCC
Ryozo Takahashi, Yusuke Kanno, Takuji Miki, Nobuhiro Kusuno, Hiroyuki Mizuno, Makoto Nagata
2024 — conf
Home Care Services in the Last Year of Life by Type of Care Management.
Nursing Informatics
Sakiko Itoh, Tomomi Sakano, Mieko Sagawa, Rie Yanagiya, Yusuke Kanno, Kayo Hirooka, Sakiko Fukui
2020 J jnl
Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Yusuke Kanno, Tadanobu Toba, Kotaro Shimamura, Nobuyasu Kanekawa
2017 J jnl
Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA.
IEICE Trans. Electron.
Makoto Saen, Tadanobu Toba, Yusuke Kanno
2014 J jnl
A Method for Measuring of RTN by Boosting Word-Line Voltage in 6-Tr-SRAMs.
IEICE Trans. Electron.
Goichi Ono, Yuki Mori, Michiaki Nakayama, Yusuke Kanno
2012 — conf
Comprehensive electrochemical imaging with local redox cycling-based electrochemical chip device for evaluation of three-dimensional culture cells.
MHS
Kosuke Ino, Mustafa Sen, Taku Nishijo, Yusuke Kanno, Hitoshi Shiku, Tomokazu Matsue
2010 J jnl
A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS.
IEEE J. Solid State Circuits
Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi
2007 J jnl
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.
IEEE J. Solid State Circuits
Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie
2007 J jnl
In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution.
IEEE J. Solid State Circuits
Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno
2006 — conf
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor.
ISSCC
Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie
2006 A* conf
Hierarchical power distribution and power management scheme for a single chip mobile processor.
DAC
Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno