Yusuke Kanazawa

11 papers B 2Journal 6Unranked 3
YearRankTypeTitle / Venue / Authors
2009 J jnl
A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS.
IEEE J. Solid State Circuits
Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Kunihiko Iizuka
2007 — conf
A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications.
CICC
Xuefeng Chen, Yan Wang, Yoshihisa Fujimoto, Pascal Lo Ré, Yusuke Kanazawa, Jesper Steensgaard, Gabor C. Temes
2006 — conf
A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique.
CICC
Yusuke Kanazawa, Yoshihisa Fujimoto, Pascal Lo Ré, Masayuki Miyamoto
2006 — conf
An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Receivers.
ISSCC
Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Masayuki Miyamoto
2005 J jnl
Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model.
Int. J. Unconv. Comput.
Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya
2004 J jnl
A MOS circuit for bursting neural oscillators with excitable oregonators.
IEICE Electron. Express
Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2004 B conf
A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection.
IJCNN
Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya
2004 J jnl
A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection.
Int. J. Robotics Autom.
Yusuke Kanazawa, Tetsuya Asai, Masayuki Ikebe, Yoshihito Amemiya
2003 J jnl
A subthreshold MOS neuron circuit based on the Volterra system.
IEEE Trans. Neural Networks
Tetsuya Asai, Yusuke Kanazawa, Yoshihito Amemiya
2003 J jnl
Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses.
J. Robotics Mechatronics
Yusuke Kanazawa, Tetsuya Asai, Yoshihito Amemiya
2002 B conf
A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology.
SMC
Yusuke Kanazawa, Takashi Yamada, Tetsuya Asai, Yoshihito Amemiya