Yusuf Leblebici

299 papers A* 5A 21B 10C 51Misc 6Journal 84Unranked 120

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS. IEEE J. Solid State Circuits Arda Uran, Kerim Türe, Cosimo Aprile, Alix Trouillet, Florian Fallegger, Emilie C. M. Revol, Azita Emami, Stéphanie P. Lacour, Catherine Dehollain, Yusuf Leblebici, Volkan Cevher
2021	—	`conf`	A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS. CICC Arda Uran, Kerim Türe, Cosimo Aprile, Alix Trouillet, Florian Fallegger, Azita Emami, Stéphanie P. Lacour, Catherine Dehollain, Yusuf Leblebici, Volkan Cevher
2021	J	`jnl`	A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI. Microelectron. J. Firat Celik, Ayca Akkaya, Yusuf Leblebici
2021	J	`jnl`	A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI. IEEE Trans. Very Large Scale Integr. Syst. Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici
2021	J	`jnl`	An 8-Bit 800 MS/s Loop-Unrolled SAR ADC With Common-Mode Adaptive Background Offset Calibration in 28 nm FDSOI. IEEE Trans. Circuits Syst. I Regul. Pap. Ayca Akkaya, Firat Celik, Yusuf Leblebici
2020	J	`jnl`	A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. IEEE J. Solid State Circuits Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf
2020	C	`conf`	A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS. ISCAS Ayca Akkaya, Firat Celik, Yusuf Leblebici
2020	C	`conf`	Discrete Time Analysis of Phase Detector Linear Range Extension in Sub-Sampling PLL. ISCAS Duygu Kostak, Yusuf Leblebici
2020	—	`conf`	Discrete Time Analysis of Phase Detector Timing Nonidealities in Type-I Sub-Sampling PLL. ICECS Duygu Kostak, Yusuf Leblebici
2020	J	`jnl`	Real-time high-resolution omnidirectional imaging platform for drone detection and tracking. J. Real Time Image Process. Bilal Demir, Selman Ergünay, Gokcen Nurlu, Vladan Popovic, Beat Ott, Peter Wellig, Jean-Philippe Thiran, Yusuf Leblebici
2019	—	`conf`	A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. ISSCC Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici
2019	—	`conf`	A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. A-SSCC Jonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici
2019	—	`conf`	A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. A-SSCC Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici
2019	—	`conf`	Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link. MWSCAS Gain Kim, Woohyun Kwon, Thomas Toifl, Yusuf Leblebici, Hyeon-Min Bae
2019	—	`conf`	ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links. NEWCAS Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici
2019	—	`conf`	JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS. PRIME Firat Celik, Ayca Akkaya, Armin Tajalli, Andreas Burg, Yusuf Leblebici
2019	—	`ch.`	Memory Effects in Multi-terminal Solid State Devices and Their Applications. Handbook of Memristor Networks Davide Sacchetto, Pierre-Emmanuel Gaillardon, Yusuf Leblebici, Giovanni De Micheli
2019	C	`conf`	Multi-ReRAM Synapses for Artificial Neural Network Training. ISCAS Irem Boybat, Cecilia Giovinazzo, Elmira Shahrabi, Igor Krawczuk, Iason Giannopoulos, Christophe Piveteau, Manuel Le Gallo, Carlo Ricciardi, Abu Sebastian, Evangelos Eleftheriou, Yusuf Leblebici
2019	—	`conf`	Non-filamentary non-volatile memory elements as synapses in neuromorphic systems. NVMTS Alessandro Fumarola, Yusuf Leblebici, Pritish Narayanan, Robert M. Shelby, L. L. Sanchez, Geoffrey W. Burr, Kibong Moon, J. Jang, Hyunsang Hwang, Severin Sidler
2019	—	`conf`	Novel 3D architecture of 1S1R. NANOARCH Behnoush Attarimashalkoubeh, Yusuf Leblebici
2019	C	`conf`	Real-Time Textureless-Region Tolerant High-Resolution Depth Estimation System. DSD Bilal Demir, Jean-Philippe Thiran, Yusuf Leblebici
2019	—	`conf`	Self-Calibrated Delay-Based LSB Extraction for Resolution Improvement in SAR ADCs. NORCAS Ayca Akkaya, Firat Celik, Yusuf Leblebici
2018	—	`conf`	A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End. NORCAS Ayca Akkaya, Firat Celik, Armin Tajalli, Yusuf Leblebici
2018	—	`conf`	A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. ISSCC Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Thomas Morf, Daniel M. Kuchta, Lukas Kull, Marcel A. Kossel, Danny Luu, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
2018	J	`jnl`	A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. IEEE J. Solid State Circuits Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
2018	—	`conf`	A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC. NEWCAS Mustafa Kilic, Yusuf Leblebici
2018	—	`conf`	A Row-Column Accessed Dynamic Element Matching DAC Architecture for SAR ADCs. NORCAS Mustafa Kilic, Selman Ergünay, Yusuf Leblebici
2018	J	`jnl`	Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants. IEEE Trans. Circuits Syst. I Regul. Pap. Cosimo Aprile, Kerim Türe, Luca Baldassarre, Mahsa Shoaran, Gürkan Yilmaz, Franco Maloberti, Catherine Dehollain, Yusuf Leblebici, Volkan Cevher
2018	J	`jnl`	An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. IEEE J. Solid State Circuits Cosimo Aprile, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl
2018	—	`conf`	An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems. CF Cosimo Aprile, Johannes Wüthrich, Luca Baldassarre, Yusuf Leblebici, Volkan Cevher
2018	J	`jnl`	Direct Reconstruction of Saturated Samples in Band-Limited OFDM Signals. CoRR Kyong Hwan Jin, Gain Kim, Yusuf Leblebici, Jong Chul Ye, Michael Unser
2018	J	`jnl`	FPGA-Based Hardware Implementation of Real-Time Optical Flow Calculation. IEEE Trans. Circuits Syst. Video Technol. Kerem Seyid, Andrea Richaud, Raffaele Capoccia, Yusuf Leblebici
2018	—	`conf`	Generalization of Referenceless Timing Mismatch Calibration Methods for Time-Interleaved ADCs. PRIME Arda Uran, Mustafa Kilic, Yusuf Leblebici
2018	C	`conf`	Hardware Implementation of a Smart Camera with Keypoint Detection and Description. ISCAS Selman Ergünay, Yusuf Leblebici
2018	—	`conf`	Impact of conductance drift on multi-PCM synaptic architectures. NVMTS Irem Boybat, S. R. Nandakumar, Manuel Le Gallo, Bipin Rajendran, Yusuf Leblebici, Abu Sebastian, Evangelos Eleftheriou
2018	B	`conf`	Online Feature Learning from a non-i.i.d. Stream in a Neuromorphic System with Synaptic Competition. IJCNN Stanislaw Wozniak, Angeliki Pantazi, Yusuf Leblebici, Evangelos Eleftheriou
2018	C	`conf`	Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. ISCAS Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl, Yusuf Leblebici
2018	—	`conf`	System Level simulation framework for the ASICs development of a novel particle physics detector. PRIME Alessandro Caratelli, Simone Scarfi, Davide Ceresa, Kostas Kloukinas, Yusuf Leblebici
2018	—	`conf`	The key impact of incorporated Al2O3 barrier layer on W-based ReRAM switching performance. PRIME Elmira Shahrabi, Cecilia Giovinazzo, Jury Sandrini, Yusuf Leblebici
2017	—	`conf`	29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. ISSCC Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
2017	J	`jnl`	A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. IEEE J. Solid State Circuits Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
2017	J	`jnl`	A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links. IEEE Trans. Circuits Syst. II Express Briefs Gain Kim, Chen Cao, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2017	—	`conf`	A hybrid CDAC - threshold configuring SAR ADC in 28nm FDSOI CMOS. NEWCAS Themistoklis G. Mavrogordatos, Mustafa Kilic, Yusuf Leblebici
2017	J	`jnl`	An Insect Eye Inspired Miniaturized Multi-Camera System for Endoscopic Imaging. IEEE Trans. Biomed. Circuits Syst. Omer Cogal, Yusuf Leblebici
2017	—	`conf`	An efficient synaptic architecture for artificial neural networks. NVMTS Irem Boybat, Manuel Le Gallo, S. R. Nandakumar, Timoleon Moraitis, Tomas Tuma, Bipin Rajendran, Yusuf Leblebici, Abu Sebastian, Evangelos Eleftheriou
2017	—	`conf`	DCT Learning-Based Hardware Design for Neural Signal Acquisition Systems. Conf. Computing Frontiers Cosimo Aprile, Johannes Wüthrich, Luca Baldassarre, Yusuf Leblebici, Volkan Cevher
2017	J	`jnl`	Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Gain Kim, Thierry Barailler, Chen Cao, Kiarash Gharibdoust, Yusuf Leblebici
2017	—	`conf`	Evolution of oxygen vacancies under electrical characterization for HfOx-based ReRAMs. ESSDERC B. Attarimashalkoubeh, Jury Sandrini, Elmira Shahrabi, Yusuf Leblebici
2017	—	`conf`	Feature Learning Using Synaptic Competition in a Dynamically-Sized Neuromorphic Architecture. ICRC Stanislaw Wozniak, Angeliki Pantazi, Yusuf Leblebici, Evangelos Eleftheriou
2017	—	`conf`	Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique. ICRC Irem Boybat, Carmelo di Nolfo, Stefano Ambrogio, Martina Bodini, Nathan C. P. Farinha, Robert M. Shelby, Pritish Narayanan, Severin Sidler, Hsinyu Tsai, Yusuf Leblebici, Geoffrey W. Burr
2017	J	`jnl`	Neuromorphic Architecture With 1M Memristive Synapses for Detection of Weakly Correlated Inputs. IEEE Trans. Circuits Syst. II Express Briefs Stanislaw Wozniak, Angeliki Pantazi, Severin Sidler, Nikolaos Papandreou, Yusuf Leblebici, Evangelos Eleftheriou
2017	J	`jnl`	Neuromorphic computing with multi-memristive synapses. CoRR Irem Boybat, Manuel Le Gallo, S. R. Nandakumar, Timoleon Moraitis, Thomas P. Parnell, Tomas Tuma, Bipin Rajendran, Yusuf Leblebici, Abu Sebastian, Evangelos Eleftheriou
2017	B	`conf`	Neuromorphic system with phase-change synapses for pattern learning and feature extraction. IJCNN Stanislaw Wozniak, Angeliki Pantazi, Yusuf Leblebici, Evangelos Eleftheriou
2017	—	`conf`	Piezoresistivity characterization of silicon nanowires through monolithic MEMS. NEMS Mohammad Nasr Esfahani, Yusuf Leblebici, B. Erdem Alaca
2017	C	`conf`	Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays. ISCAS Pritish Narayanan, Lucas L. Sanches, Alessandro Fumarola, Robert M. Shelby, Stefano Ambrogio, Jun-Woo Jang, Hyunsang Hwang, Yusuf Leblebici, Geoffrey W. Burr
2017	J	`jnl`	Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies. Integr. Can Baltaci, Yusuf Leblebici
2017	—	`conf`	Unsupervised Learning Using Phase-Change Synapses and Complementary Patterns. ICANN (1) Severin Sidler, Angeliki Pantazi, Stanislaw Wozniak, Yusuf Leblebici, Evangelos Eleftheriou
2016	—	`conf`	A 16-channel 1.1mm VLSI Circuits Mahsa Shoaran, Masoud Shahshahani, Masoud Farivar, Joyel Almajano, Amirhossein Shahshahani, Alexandre Schmid, Anatol Bragin, Yusuf Leblebici, Azita Emami
2016	J	`jnl`	A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects. IEEE J. Solid State Circuits Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2016	J	`jnl`	A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces. IEEE Trans. Circuits Syst. II Express Briefs Gain Kim, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2016	C	`conf`	A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces. ISCAS Kiarash Gharibdoust, Gain Kim, Armin Tajalli, Yusuf Leblebici
2016	—	`conf`	A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS. NEWCAS Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2016	—	`conf`	Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data links. APCCAS Gain Kim, Yusuf Leblebici
2016	C	`conf`	Block matching based real-time optical flow hardware implementation. ISCAS Kerem Seyid, Andrea Richaud, Raffaele Capoccia, Yusuf Leblebici
2016	J	`jnl`	Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. Jury Sandrini, Marios Barlas, Maxime Thammasack, Tugba Demirci, Michele De Marchi, Davide Sacchetto, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Yusuf Leblebici
2016	—	`conf`	Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique. 3DIC S. E. Kucuk Eroglu, W. Y. Choo, Yusuf Leblebici
2016	—	`conf`	Design and Implementation of Real-Time Multi-sensor Vision Systems. ACM Great Lakes Symposium on VLSI Yusuf Leblebici
2016	J	`jnl`	Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs. Microelectron. J. Giulia Beanato, Kiarash Gharibdoust, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici
2016	—	`conf`	F1: Designing secure systems: Manufacturing, circuits and architectures. ISSCC Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata
2016	J	`jnl`	Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors. Microelectron. J. Giulia Beanato, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici
2016	J	`jnl`	Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. IEEE J. Solid State Circuits Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
2016	—	`conf`	Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response. ESSDERC Severin Sidler, Irem Boybat, Robert M. Shelby, Pritish Narayanan, Jun-Woo Jang, Alessandro Fumarola, Kibong Moon, Yusuf Leblebici, Hyunsang Hwang, Geoffrey W. Burr
2016	—	`conf`	Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition. ACM Great Lakes Symposium on VLSI Cosimo Aprile, Luca Baldassarre, Vipul Gupta, Juhwan Yoo, Mahsa Shoaran, Yusuf Leblebici, Volkan Cevher
2016	J	`jnl`	Multi-camera platform for panoramic real-time HDR video construction and rendering. J. Real Time Image Process. Vladan Popovic, Kerem Seyid, Eliéva Pignat, Ömer Çogal, Yusuf Leblebici
2016	J	`jnl`	Review of advances in neural networks: Neural design technology stack. Neurocomputing Adela-Diana Almasi, Stanislaw Wozniak, Valentin Cristea, Yusuf Leblebici, Ton Engbersen
2015	—	`conf`	10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS. ISSCC Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2015	—	`conf`	3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation. NORCAS Hasene Gulperi Ozsema, Tugba Demirci, Yusuf Leblebici
2015	—	`conf`	A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS. VLSIC Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2015	—	`conf`	A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. VLSIC Alessandro Cevrero, Cosimo Aprile, Pier Andrea Francese, Urs Bapst, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Hazar Yueksel, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl
2015	J	`jnl`	A Real-Time Multiaperture Omnidirectional Visual Sensor Based on an Interconnected Network of Smart Cameras. IEEE Trans. Circuits Syst. Video Technol. Kerem Seyid, Vladan Popovic, Omer Cogal, Abdulkadir Akin, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici
2015	J	`jnl`	A comparative experimental investigation on responsivity and response speed of photo-diode and photo-BJT structures integrated in a low-cost standard CMOS process. Microelectron. J. Nikola Katic, Alexandre Schmid, Yusuf Leblebici
2015	B	`conf`	A low-power 490 mpixels/s hardware accelerator for pyramidal decomposition of images. ICIP Vladan Popovic, Yusuf Leblebici
2015	—	`conf`	A novel hybrid architecture for real-time omnidirectional image reconstruction. ICDSC Selman Ergünay, Vladan Popovic, Kerem Seyid, Yusuf Leblebici
2015	J	`jnl`	A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder. Microelectron. J. Nikola Katic, Radisav Cojbasic, Alexandre Schmid, Yusuf Leblebici
2015	J	`jnl`	A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces. Int. J. Circuit Theory Appl. Nikola Katic, Ibrahim Kazi, Armin Tajalli, Alexandre Schmid, Yusuf Leblebici
2015	A	`conf`	A ultra-low-power FPGA based on monolithically integrated RRAMs. DATE Pierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2015	J	`jnl`	Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Alexandre Schmid, Yusuf Leblebici
2015	J	`jnl`	Compressive image acquisition in modern CMOS IC design. Int. J. Circuit Theory Appl. Nikola Katic, Mahdad Hosseini Kamal, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici
2015	C	`conf`	Design of high-temperature SRAM for reliable operation beyond 250°C. ISCAS Radisav Cojbasic, Yusuf Leblebici
2015	C	`conf`	Design optimization of polyphase digital down converters for extremely high frequency wireless communications. VLSI-SoC Gain Kim, Raffaele Capoccia, Yusuf Leblebici
2015	—	`conf`	FIR filters for hardware-based real-time multi-band image blending. Real-Time Image and Video Processing Vladan Popovic, Yusuf Leblebici
2015	—	`conf`	Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology. NORCAS Hasene Gulperi Ozsema, Duygu Kostak, Tugba Demirci, Yusuf Leblebici
2015	C	`conf`	Hardware implementation of real-time multiple frame super-resolution. VLSI-SoC Kerem Seyid, Sebastien Blanc, Yusuf Leblebici
2015	J	`jnl`	Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces. IEEE J. Solid State Circuits Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
2015	C	`conf`	Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators. ISCAS Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Yusuf Leblebici
2015	C	`conf`	Live demonstration: Real-time free viewpoint synthesis using three-camera disparity estimation hardware. ISCAS Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Jonathan Masur, Alexandre Schmid, Yusuf Leblebici
2015	C	`conf`	Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology. ISCAS Jury Sandrini, Tugba Demirci, Maxime Thammasack, Davide Sacchetto, Yusuf Leblebici
2015	C	`conf`	Real-time free viewpoint synthesis using three-camera disparity estimation hardware. ISCAS Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Jonathan Masur, Alexandre Schmid, Yusuf Leblebici
2015	—	`conf`	Structured sampling and recovery of iEEG signals. CAMSAP Luca Baldassarre, Cosimo Aprile, Mahsa Shoaran, Yusuf Leblebici, Volkan Cevher
2015	—	`conf`	Trinocular adaptive window size disparity estimation algorithm and its real-time hardware. VLSI-DAT Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Ipek Baz, Alexandre Schmid, Yusuf Leblebici
2014	—	`conf`	22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS. ISSCC Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
2014	—	`conf`	3D serial TSV link for low-power chip-to-chip communication. ICICDT Giulia Beanato, Alessandro Cevrero, Giovanni De Micheli, Yusuf Leblebici
2014	—	`conf`	A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm A-SSCC Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
2014	—	`conf`	A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces. NORCHIP Nikola Katic, Ibrahim Kazi, Armin Tajalli, Alexandre Schmid, Yusuf Leblebici
2014	—	`conf`	A retina-inspired robust on-focal-plane multi-band edge-detection scheme for CMOS image sensors. MWSCAS Nikola Katic, Alexandre Schmid, Yusuf Leblebici
2014	C	`conf`	An Immersive Telepresence System Using a Real-Time Omnidirectional Camera and a Virtual Reality Head-Mounted Display. ISM Luis Manuel Gaemperle, Kerem Seyid, Vladan Popovic, Yusuf Leblebici
2014	J	`jnl`	Dynamically adaptive real-time disparity estimation hardware using iterative refinement. Integr. Abdulkadir Akin, Ipek Baz, Alexandre Schmid, Yusuf Leblebici
2014	J	`jnl`	Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design. IEEE Trans. Circuits Syst. I Regul. Pap. Ibrahim Kazi, Pascal Andreas Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Yusuf Leblebici, Andreas Peter Burg, Giovanni De Micheli
2014	J	`jnl`	Image Blending in a High Frame Rate FPGA-based Multi-Camera System. J. Signal Process. Syst. Vladan Popovic, Kerem Seyid, Abdulkadir Akin, Ömer Çogal, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici
2014	—	`conf`	Parallel vs. serial inter-plane communication using TSVs. LASCAS Somayyeh Rahimian Omam, Yusuf Leblebici, Giovanni De Micheli
2014	J	`jnl`	Performance Optimization and FPGA Implementation of Real-Time Tone Mapping. IEEE Trans. Circuits Syst. II Express Briefs Vladan Popovic, Eliéva Pignat, Yusuf Leblebici
2014	—	`conf`	Programmable active pixel sensor for low-light biomedical applications. BioCAS Gozen Koklu, Yusuf Leblebici, Giovanni De Micheli, Sandro Carrara
2014	—	`conf`	Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras. VLSI-SoC (Selected Papers) Kerem Seyid, Ömer Çogal, Vladan Popovic, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici
2014	C	`conf`	Reconfigurable forward homography estimation system for real-time applications. VLSI-SoC Vladan Popovic, Yusuf Leblebici
2013	A	`conf`	3D-MMC: a modular 3D multi-core architecture with efficient resource pooling. DATE Tiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse K. Coskun, Yusuf Leblebici
2013	—	`conf`	A 16-channel, 359 μW, parallel neural recording system using Walsh-Hadamard coding. CICC Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici
2013	J	`jnl`	A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. IEEE J. Solid State Circuits Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
2013	—	`conf`	A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. ISSCC Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
2013	J	`jnl`	A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA. J. Low Power Electron. Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici
2013	—	`conf`	A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware. ACM Great Lakes Symposium on VLSI Abdulkadir Akin, Ipek Baz, Baris Atakan, Irem Boybat, Alexandre Schmid, Yusuf Leblebici
2013	C	`conf`	A low-power area-efficient compressive sensing approach for multi-channel neural recording. ISCAS Mahsa Shoaran, Mariazel Maqueda Lopez, Vijaya Sankara Rao Pasupureddi, Yusuf Leblebici, Alexandre Schmid
2013	C	`conf`	Characterization of standard CMOS compatible photodiodes and pixels for Lab-on-Chip devices. ISCAS Gozen Koklu, Ralph Etienne-Cummings, Yusuf Leblebici, Giovanni De Micheli, Sandro Carrara
2013	—	`conf`	Column-separated compressive sampling scheme for low power CMOS image sensors. NEWCAS Nikola Katic, Mahdad Hosseini Kamal, Mustafa Kilic, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici
2013	C	`conf`	Compressed look-up-table based real-time rectification hardware. VLSI-SoC Abdulkadir Akin, Ipek Baz, Luis Manuel Gaemperle, Alexandre Schmid, Yusuf Leblebici
2013	Misc	`conf`	Compressive multichannel cortical signal recording. ICASSP Mahdad Hosseini Kamal, Mahsa Shoaran, Yusuf Leblebici, Alexandre Schmid, Pierre Vandergheynst
2013	—	`conf`	Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware. VLSI-SoC (Selected Papers) Abdulkadir Akin, Luis Manuel Gaemperle, Halima Najibi, Alexandre Schmid, Yusuf Leblebici
2013	A	`conf`	Fast and accurate BER estimation methodology for I/O links based on extreme value theory. DATE Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis
2013	—	`conf`	FireBird: PowerPC e200 based SoC for high temperature operation. CICC Radisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder, Andreas Burg, Yusuf Leblebici
2013	J	`jnl`	Hemispherical Multiple Camera System for High Resolution Omni-Directional Light Field Imaging. IEEE J. Emerg. Sel. Topics Circuits Syst. Abdulkadir Akin, Omer Cogal, Kerem Seyid, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici
2013	—	`conf`	High frame-rate low-power compressive sampling CMOS image sensor architecture: [extended abstract]. ACM Great Lakes Symposium on VLSI Nikola Katic, Mahdad Hosseini Kamal, Mustafa Kilic, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici
2013	—	`conf`	Integration of intra chip stack fluidic cooling using thin-layer solder bonding. 3DIC Yassir Madhour, Michael Zervas, Gerd Schlottig, Thomas Brunschwiler, Yusuf Leblebici, John Richard Thome, Bruno Michel
2013	—	`conf`	Interconnected network of cameras. Sensors, Cameras, and Systems for Industrial and Scientific Applications Mahdad Hosseini Kamal, Hossein Afshari, Yusuf Leblebici, Alexandre Schmid, Pierre Vandergheynst
2013	—	`conf`	Power-efficient CMOS image acquisition system based on compressive sampling. MWSCAS Nikola Katic, Mahdad Hosseini Kamal, Mustafa Kilic, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici
2013	Misc	`conf`	Real-time hardware implementation of multi-resolution image blending. ICASSP Vladan Popovic, Kerem Seyid, Alexandre Schmid, Yusuf Leblebici
2013	C	`conf`	Spherical Panorama Construction Using Multi Sensor Registration Priors and Its Real-Time Hardware. ISM Omer Cogal, Vladan Popovic, Yusuf Leblebici
2013	J	`jnl`	The PANOPTIC Camera: A Plenoptic Sensor with Real-Time Omnidirectional Capability. J. Signal Process. Syst. Hossein Afshari, Laurent Jacques, Luigi Bagnato, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici
2013	A*	`conf`	Towards structured ASICs using polarity-tunable Si nanowire transistors. DAC Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amarù, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2013	A	`conf`	Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. DATE Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2012	C	`conf`	3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory. VLSI-SoC Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini
2012	J	`jnl`	A spherical multi-camera system with real-time omnidirectional video acquisition capability. IEEE Trans. Consumer Electron. Hossein Afshari, Vladan Popovic, Tugce Tasci, Alexandre Schmid, Yusuf Leblebici
2012	—	`conf`	An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements. VLSIC Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici, Jan M. Rabaey
2012	—	`conf`	Configurable Low-Latency Interconnect for Multi-core Clusters. VLSI-SoC (Selected Papers) Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini
2012	C	`conf`	Design and Implementation of Multi-camera Systems Distributed over a Spherical Geometry. Diagrams Hossein Afshari, Kerem Seyid, Alexandre Schmid, Yusuf Leblebici
2012	J	`jnl`	Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. Giulia Beanato, Paolo Giovannini, Alessandro Cevrero, Panagiotis Athanasopoulos, Michael Zervas, Yuksel Temiz, Yusuf Leblebici
2012	—	`conf`	Design techniques and analysis of high-resolution neural recording systems targeting epilepsy focus localization. EMBC Mahsa Shoaran, Claudio Pollo, Yusuf Leblebici, Alexandre Schmid
2012	C	`conf`	Enhanced Omnidirectional Image Reconstruction Algorithm and Its Real-Time Hardware. DSD Abdulkadir Akin, Elif Erdede, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici
2012	C	`conf`	GMS: Generic memristive structure for non-volatile FPGAs. VLSI-SoC Pierre-Emmanuel Gaillardon, Davide Sacchetto, Shashikanth Bobba, Yusuf Leblebici, Giovanni De Micheli
2012	J	`jnl`	High-Level Energy Estimation in the Sub-V$_{{\rm T}}$ Domain: Simulation and Measurement of a Cardiac Event Detector. IEEE Trans. Biomed. Circuits Syst. Omer Can Akgun, Joachim Neves Rodrigues, Yusuf Leblebici, Viktor Öwall
2012	J	`jnl`	Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review. Proc. IEEE Davide Sacchetto, Giovanni De Micheli, Yusuf Leblebici
2012	A*	`conf`	Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors. DAC Shashikanth Bobba, Michele De Marchi, Yusuf Leblebici, Giovanni De Micheli
2012	—	`conf`	Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors. NANOARCH Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Jian Zhang, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2012	C	`conf`	Quantitative comparison of commercial CCD and custom-designed CMOS camera for biological applications. ISCAS Gozen Koklu, Julien Ghaye, Rene Beuchat, Giovanni De Micheli, Yusuf Leblebici, Sandro Carrara
2012	—	`conf`	Real-Time FPGA Implementation of Linear Blending Vision Reconstruction Algorithm Using a Spherical Light Field Camera. SiPS Hossein Afshari, Abdulkadir Akin, Vladan Popovic, Alexandre Schmid, Yusuf Leblebici
2012	J	`jnl`	Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL. IEEE Trans. Circuits Syst. II Express Briefs Armin Tajalli, Yusuf Leblebici
2011	A	`conf`	Alternative design methodologies for the next generation logic switch. ICCAD Davide Sacchetto, Michele De Marchi, Giovanni De Micheli, Yusuf Leblebici
2011	J	`jnl`	Amplitude modulation based readout for very dense active microelectrode arrays. IEICE Electron. Express Neil Joye, Alexandre Schmid, Yusuf Leblebici
2011	C	`conf`	Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders. ISCAS Christoph Roth, Alessandro Cevrero, Christoph Studer, Yusuf Leblebici, Andreas Burg
2011	J	`jnl`	Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Armin Tajalli, Yusuf Leblebici
2011	—	`conf`	Design trade-offs in ultra-low-power CMOS and STSCL digital systems. ECCTD Armin Tajalli, Yusuf Leblebici
2011	J	`jnl`	Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor. IEEE Trans. Biomed. Circuits Syst. Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici
2011	—	`conf`	Hardware security in VLSI. ACM Great Lakes Symposium on VLSI Wayne P. Burleson, Yusuf Leblebici
2011	J	`jnl`	Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter. IEEE Trans. Circuits Syst. II Express Briefs Armin Tajalli, Yusuf Leblebici
2011	J	`jnl`	Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing. J. Low Power Electron. Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici
2011	—	`conf`	PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status. FMCO Christian Fabre, Iuliana Bacivarov, Ananda Basu, Martino Ruggiero, David Atienza, Eric Flamand, Jean-Pierre Krimm, Julien Mottin, Lars Schor, Pratyush Kumar, Hoeseok Yang, Devesh B. Chokshi, Lothar Thiele, Saddek Bensalem, Marius Bozga, Luca Benini, Mohamed M. Sabry, Yusuf Leblebici, Giovanni De Micheli, Diego Melpignano
2011	A*	`conf`	Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. DAC Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici
2011	A	`conf`	Towards thermally-aware design of 3D MPSoCs with inter-tier cooling. DATE Mohamed M. Sabry, Arvind Sridhar, David Atienza, Yuksel Temiz, Yusuf Leblebici, S. Szczukiewicz, Navid Borhani, John Richard Thome, Thomas Brunschwiler, Bruno Michel
2010	C	`conf`	A (256×256) pixel 76.7mW CMOS imager/ compressor based on real-time In-pixel compressive sensing. ISCAS Vahid Majidzadeh, Laurent Jacques, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici
2010	—	`conf`	A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems. ESSCIRC Armin Tajalli, Yusuf Leblebici
2010	A	`conf`	AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics. DATE Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici
2010	J	`jnl`	Capacitance DNA bio-chips improved by new probe immobilization strategies. Microelectron. J. Sandro Carrara, Andrea Cavallini, Yusuf Leblebici, Giovanni De Micheli, Vijayender Bhalla, Francesco Valle, Bruno Samorì, Luca Benini, Bruno Riccò, Inger Vikholm-Lundin, Tony Munter
2010	C	`conf`	Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs. VLSI-SoC Fengda Sun, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici
2010	C	`conf`	Design aspects of carry lookahead adders with vertically-stacked nanowire transistors. ISCAS Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici
2010	J	`jnl`	Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields. IET Inf. Secur. Deniz Karakoyunlu, Frank Kagan Gürkaynak, Berk Sunar, Yusuf Leblebici
2010	—	`conf`	Integrating bio-sensing functions on CMOS chips. APCCAS Carlotta Guiducci, Yuksel Temiz, Yusuf Leblebici, Enrico Accastelli, Anna Ferretti, Giulia Cappi, Elena Bianchi
2010	—	`conf`	Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random V PATMOS Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici
2010	C	`conf`	Memristive devices fabricated with silicon nanowire schottky barrier transistors. ISCAS Davide Sacchetto, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli, Yusuf Leblebici
2010	J	`jnl`	Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits. J. Low Power Electron. Armin Tajalli, Yusuf Leblebici
2010	J	`jnl`	Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff. Microelectron. J. Massimo Alioto, Stéphane Badel, Yusuf Leblebici
2010	C	`conf`	Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation. VLSI-SoC Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici
2010	C	`conf`	Selective redundancy-based design techniques for the minimization of local delay variations. ISCAS Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici
2010	—	`conf`	Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution. ESSCIRC Armin Tajalli, Yusuf Leblebici
2010	A	`conf`	Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. DATE Armin Tajalli, Yusuf Leblebici
2009	A	`conf`	3D configuration caching for 2D FPGAs. FPGA Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj
2009	A	`conf`	A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	J	`jnl`	A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation. Int. J. Nanotechnol. Mol. Comput. Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici
2009	J	`jnl`	A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology. IEEE J. Solid State Circuits Armin Tajalli, Yusuf Leblebici
2009	J	`jnl`	A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime. Int. J. Circuit Theory Appl. Omer Can Akgun, Frank K. Gürkaynak, Yusuf Leblebici
2009	—	`conf`	A flexible DSP block to enhance FPGA arithmetic performance. FPT Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	—	`conf`	A fully on-chip LDO voltage regulator for remotely powered cortical implants. ESSCIRC Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici
2009	—	`conf`	A micropower neural recording amplifier with improved noise efficiency factor. ECCTD Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici
2009	B	`conf`	A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. IJCNN Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya
2009	—	`conf`	A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories. ASP-DAC M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli
2009	—	`conf`	A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold. CICC Armin Tajalli, Yusuf Leblebici
2009	C	`conf`	Analysis and Design of Ultra-low Power Subthreshold MCML Gates. ISCAS Massimo Alioto, Yusuf Leblebici
2009	Misc	`conf`	CMOS compressed imaging by Random Convolution. ICASSP Laurent Jacques, Pierre Vandergheynst, Alexandre Bibet, Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici
2009	Misc	`conf`	Complete nanowire crossbar framework optimized for the multi-spacer patterning technique. CASES M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf Leblebici, Giovanni De Micheli
2009	A*	`conf`	Decoding nanowire arrays fabricated with the multi-spacer patterning technique. DAC M. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De Micheli
2009	A	`conf`	Dynamic thermal management in 3D multicore architectures. DATE Ayse K. Coskun, José L. Ayala, David Atienza, Tajana Simunic Rosing, Yusuf Leblebici
2009	J	`jnl`	Electrical modeling of the cell-electrode interface for recording neural activity from high-density microelectrode arrays. Neurocomputing Neil Joye, Alexandre Schmid, Yusuf Leblebici
2009	—	`conf`	Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V PATMOS Joachim Neves Rodrigues, Omer Can Akgun, Puneet Acharya, Adolfo de la Calle, Yusuf Leblebici, Viktor Öwall
2009	J	`jnl`	Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Trans. Comput. Sci. Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
2009	J	`jnl`	Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	J	`jnl`	Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits. IEEE Trans. Circuits Syst. II Express Briefs Armin Tajalli, Massimo Alioto, Yusuf Leblebici
2009	J	`jnl`	Leakage Current Reduction Using Subthreshold Source-Coupled Logic. IEEE Trans. Circuits Syst. II Express Briefs Armin Tajalli, Yusuf Leblebici
2009	C	`conf`	Load Optimization of an Inductive Power Link for Remote Powering of Biomedical Implants. ISCAS Kanber Mithat Silay, Denis Dondi, Luca Larcher, Michel J. Declercq, Luca Benini, Yusuf Leblebici, Catherine Dehollain
2009	A	`conf`	Memory organization and data layout for instruction set extensions with architecturally visible storage. ICCAD Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	J	`jnl`	On the Reliability of Post-CMOS and SET Systems. Int. J. Nanotechnol. Mol. Comput. Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici
2009	—	`conf`	Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR). DFT Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici
2009	—	`conf`	Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth. NanoNet Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici
2009	C	`conf`	Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff. ISCAS Massimo Alioto, Stéphane Badel, Yusuf Leblebici
2009	—	`conf`	Subthreshold Circuit Design for Ultra-Low-Power Applications. PATMOS Yusuf Leblebici
2009	C	`conf`	Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design. ISCAS Armin Tajalli, Yusuf Leblebici
2009	—	`conf`	Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems. ESSCIRC Armin Tajalli, Yusuf Leblebici
2009	—	`conf`	Through Silicon Via-Based Grid for Thermal Control in 3D Chips. NanoNet José L. Ayala, Arvind Sridhar, Vinod Pangracious, David Atienza, Yusuf Leblebici
2009	J	`jnl`	Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP. Microelectron. J. Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici
2009	B	`conf`	Using 3D integration technology to realize multi-context FPGAs. FPL Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	—	`conf`	Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks. 3DIC Thomas Brunschwiler, Stephan Paredes, Ute Drechsler, Bruno Michel, W. Cesar, G. Töral, Yuksel Temiz, Yusuf Leblebici
2008	—	`conf`	A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology. APCCAS Thomas Liechti, Armin Tajalli, Omer Can Akgun, Zeynep Toprak Deniz, Yusuf Leblebici
2008	A	`conf`	A Generic Standard Cell Design Methodology for Differential Circuit Styles. DATE Stéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici
2008	A	`conf`	Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
2008	J	`jnl`	CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications. Microelectron. J. Stéphane Badel, Alexandre Schmid, Yusuf Leblebici
2008	Misc	`conf`	Design space exploration for field programmable compressor trees. CASES Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
2008	J	`jnl`	Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime. J. Low Power Electron. Omer Can Akgun, Yusuf Leblebici
2008	—	`conf`	Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. PATMOS Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici
2008	C	`conf`	Improving the power-delay product in SCL circuits using source follower output stage. ISCAS Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer
2008	A	`conf`	Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. DATE Carlotta Guiducci, Alexandre Schmid, Frank K. Gürkaynak, Yusuf Leblebici
2008	A*	`conf`	Programmable logic circuits based on ambipolar CNFET. DAC M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli
2008	—	`conf`	Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs. PATMOS Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici
2008	J	`jnl`	Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications. IEEE J. Solid State Circuits Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici, Eric A. Vittoz
2008	J	`jnl`	Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli
2007	—	`conf`	A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density. Nano-Net Milos Stanisavljevic, Frank Kagan Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani
2007	J	`jnl`	A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication. IEEE J. Solid State Circuits Armin Tajalli, Paul Muller, Yusuf Leblebici
2007	—	`conf`	A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. ICSAMOS Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
2007	C	`conf`	Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage. ISCAS Stéphane Badel, Yusuf Leblebici
2007	—	`conf`	Current sensing completion detection for subthreshold asynchronous circuits. ECCTD Omer Can Akgun, Yusuf Leblebici, Eric A. Vittoz
2007	—	`conf`	Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. ACM Great Lakes Symposium on VLSI Milos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani
2007	—	`conf`	Early wire characterization for predictable network-on-chip global interconnects. SLIP Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli
2007	A	`conf`	Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. ICCAD M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli
2007	J	`jnl`	On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation. IEEE J. Solid State Circuits Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz
2007	—	`conf`	Predictable system interconnects through accurate early wire characterization. SoCC I. Hatyrnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici
2007	J	`jnl`	Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit CoRR Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici
2007	J	`jnl`	Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits. J. Low Power Electron. Armin Tajalli, Paul Muller, Yusuf Leblebici
2007	—	`conf`	Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. ESSCIRC Armin Tajalli, Eric A. Vittoz, Yusuf Leblebici, Elizabeth J. Brauer
2006	C	`conf`	A Predictable Communication Scheme for Embedded Multiprocessor Systems. VLSI-SoC Mehmet Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici
2006	—	`conf`	A simulation methodology for reliability analysis in multi-core SoCs. ACM Great Lakes Symposium on VLSI Ayse K. Coskun, Tajana Simunic Rosing, Yusuf Leblebici, Giovanni De Micheli
2006	J	`jnl`	Analysis and Optimization of MPSoC Reliability. J. Low Power Electron. Ayse Kivilcim Coskun, Tajana Simunic, Kresimir Mihic, Giovanni De Micheli, Yusuf Leblebici
2006	C	`conf`	Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. ISCAS Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici
2006	C	`conf`	Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. VLSI-SoC Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz
2006	—	`conf`	Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. VLSI-SoC (Selected Papers) Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz
2006	B	`conf`	Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density. IJCNN Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici
2006	C	`conf`	Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. VLSI-SoC Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer
2006	C	`conf`	Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. ISCAS Elizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici
2006	C	`conf`	Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range. ISCAS Omer Can Akgun, Yusuf Leblebici
2005	C	`conf`	A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis. VLSI-SoC Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici
2005	A	`conf`	A low-power, multichannel gated oscillator-based CDR for short-haul applications. ISLPED Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici
2005	—	`conf`	A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology. ESSCIRC Armin Tajalli, Paul Muller, Mojtaba Atarodi, Yusuf Leblebici
2005	—	`conf`	CONAN - A Design Exploration Framework for Reliable Nano-Electronics. ASAP Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, Antonio Rubio
2005	—	`conf`	Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. ESTIMedia Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici
2005	C	`conf`	Jitter Tolerance Analysis of Clock and Data Recovery Circuits. FDL Paul Muller, Yusuf Leblebici
2005	—	`conf`	Limiting amplifiers for next-generation multi-channel optical I/0 interfaces in SoCs. SoCC Paul Muller, Yusuf Leblebici
2005	—	`conf`	Low-power current mode logic for improved DPA-resistance in embedded systems. ISCAS (2) Zeynep Toprak Deniz, Yusuf Leblebici
2005	J	`jnl`	On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electron. Express Takahide Oya, Alexandre Schmid, Tetsuya Asai, Yusuf Leblebici, Yoshihito Amemiya
2005	—	`conf`	Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. ISCAS (2) Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne
2005	—	`conf`	Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. ISCAS (3) Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici
2005	A	`conf`	Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. DATE Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici
2004	—	`conf`	A 4-channel 2.5Gb/s/channel 66dBΩ inductorless transimpedance amplifier [optical receiver applications]. ESSCIRC Paul Muller, Yusuf Leblebici, Matthew K. Emsley, M. Selim Ünlü
2004	—	`conf`	A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies. DFT Alexandre Schmid, Yusuf Leblebici
2004	B	`conf`	Fault-tolerant PLA-style circuit design for failure-prone nanometer CMOS and quantum device technologies. IJCNN Alexandre Schmid, Yusuf Leblebici
2004	—	`conf`	Low noise MCML prefix adders using 0.18 µm CMOS technology. Circuits, Signals, and Systems Elizabeth J. Brauer, Yusuf Leblebici
2004	—	`conf`	Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture. ISCAS (5) Stéphane Badel, Alexandre Schmid, Yusuf Leblebici
2004	—	`conf`	Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction. ISCAS (5) Ilhan Hatirnaz, Yusuf Leblebici
2004	—	`conf`	Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities. SoC Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne
2004	—	`conf`	Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors. ISCAS (3) Alexandre Schmid, Yusuf Leblebici
2004	J	`jnl`	Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors. IEEE Trans. Very Large Scale Integr. Syst. Alexandre Schmid, Yusuf Leblebici
2004	—	`conf`	Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic. Circuits, Signals, and Systems Elizabeth J. Brauer, Yusuf Leblebici
2003	B	`conf`	A VLSI Hamming artificial neural network with k-winner-take-all and k-loser-take-all capability. IJCNN Stéphane Badel, Alexandre Schmid, Yusuf Leblebici
2003	—	`conf`	Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology. ISCAS (1) Zeynep Toprak Deniz, Yusuf Leblebici
2003	—	`conf`	Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity. ISCAS (5) Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici
2003	—	`conf`	Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation. SoC Ilhan Hatirnaz, Yusuf Leblebici
2003	B	`conf`	VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications. ESANN Stéphane Badel, Alexandre Schmid, Yusuf Leblebici
2000	J	`jnl`	A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic. VLSI Design Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici
2000	Misc	`conf`	A compact modular architecture for high-speed binary sorting. ICASSP Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici
2000	C	`conf`	A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering. ISCAS Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici
2000	C	`conf`	Higher radix Kogge-Stone parallel prefix adder architectures. ISCAS Frank K. Gürkaynak, Yusuf Leblebici, Laurent Chaouat, Patrik J. McGuinness
1999	—	`conf`	A novel analog-digital flash converter architecture based on capacitive threshold gates. ISCAS (2) Alexandre Schmid, D. Bowler, R. Baumgartner, Yusuf Leblebici
1999	B	`conf`	A two-stage charge-based analog/digital neuron circuit with adjustable weights. IJCNN Alexandre Schmid, Yusuf Leblebici, Daniel Mlynek
1999	—	`conf`	Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. ISCAS (1) Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici
1996	J	`jnl`	A capacitive threshold-logic gate. IEEE J. Solid State Circuits Hakan Özdemir, Asim Kepkep, Banu Pamir, Yusuf Leblebici, Ugur Çilingiroglu
1996	J	`jnl`	A compact high-speed (31, 5) parallel counter circuit based on capacitive threshold-logic gates. IEEE J. Solid State Circuits Yusuf Leblebici, Hakan Özdemir, Asim Kepkep, Ugur Çilingiroglu
1996	J	`jnl`	Design considerations for CMOS digital circuits with improved hot-carrier reliability. IEEE J. Solid State Circuits Yusuf Leblebici
1993	J	`jnl`	ILLIADS: a fast timing and reliability simulator for digital MOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang
1993	J	`jnl`	Modeling and simulation of hot-carrier-induced device degradation in MOS circuits. IEEE J. Solid State Circuits Yusuf Leblebici, Sung-Mo Kang
1992	J	`jnl`	Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yusuf Leblebici, Sung-Mo Kang
1991	J	`jnl`	An accurate analytical delay model for BiCMOS driver circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Carlos H. Díaz, Sung-Mo Kang, Yusuf Leblebici
1991	—	`—`	Modeling and simulation of hot-carrier induced device and circuit degradation for VLSI reliability Yusuf Leblebici
1991	A	`conf`	New Simulation Methods for MOS VLSI Timing and Reliability. ICCAD Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang
1990	A	`conf`	An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. ICCAD Yusuf Leblebici, Sung-Mo Kang
1989	C	`conf`	Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability. ICCD Yusuf Leblebici, Sung-Mo Kang
1988	A	`conf`	An efficient method for circuit sensitivity calculation using piecewise linear waveform models. ICCAD Sung-Mo Kang, Yusuf Leblebici