Yuriy M. Greshishchev

16 papers B 1Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2023 J jnl
Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium.
IEEE J. Solid State Circuits
Yuriy M. Greshishchev
2019 — conf
A 60 GS/s 8-b DAC with > 29.5dB SINAD up to Nyquist frequency in 7nm FinFET CMOS.
BCICTS
Yuriy M. Greshishchev, Tingjun Wen, Naim Ben-Hamida, Jorge Aguirre, Sadok Aouini, Marinette Besson, Robert Gibbins, Young Gouk Cho, Jerry Lam, Douglas McPherson, Mahdi Parvizi
2019 — conf
Coherent Transceiver for High Speed Optical Communications: Opportunities and Challenges.
BCICTS
Sebastien Blais, Yuriy M. Greshishchev, Peter Schvan, Ian Betty, Douglas McGhan
2011 — conf
A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory.
ISSCC
Yuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang, Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan
2010 — conf
A 40GS/s 6b ADC in 65nm CMOS.
ISSCC
Yuriy M. Greshishchev, Jorge Aguirre, Marinette Besson, Robert Gibbins, Chris Falt, Philip Flemke, Naim Ben-Hamida, Daniel Pollex, Peter Schvan, Shing-Chi Wang
2010 — conf
Transceiver circuits for optical communications.
ISSCC
Yuriy M. Greshishchev, Franz Dielacher, Michael Flynn, Donhee Ham, Naresh R. Shanbhag, Takuji Yamamoto
2009 — conf
Clock recovery for a 40 Gb/s QPSK optical receiver.
ICECS
Naim Ben-Hamida, John Sitch, Philip Flemke, Daniel Pollex, Peter Schvan, Yuriy M. Greshishchev, Shing-Chi Wang, Chris Falt
2008 — conf
A 24GS/s 6b ADC in 90nm CMOS.
ISSCC
Peter Schvan, Jérôme Bach, Chris Falt, Philip Flemke, Robert Gibbins, Yuriy M. Greshishchev, Naim Ben-Hamida, Daniel Pollex, John Sitch, Shing-Chi Wang, John Wolczanski
2008 — conf
Trends and Challenges in Optical Communications Front-End.
ISSCC
Yuriy M. Greshishchev, Takuji Yamamoto, Naresh R. Shanbhag
2007 — conf
Optical Communications.
ISSCC
Sung Min Park, Yuriy M. Greshishchev
2005 J jnl
Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits
Axel Thomsen, Jacques Christophe Rudell, Yuriy M. Greshishchev, J. E. D. Hurwitz
2000 J jnl
A fully integrated SiGe receiver IC for 10-Gb/s data rate.
IEEE J. Solid State Circuits
Yuriy M. Greshishchev, Peter Schvan, Jonathan L. Showell, Mu-Liang Xu, Jugnu J. Ojha, Jonathan E. Rogers
2000 J jnl
SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application.
IEEE J. Solid State Circuits
Yuriy M. Greshishchev, Peter Schvan
1999 J jnl
A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifier.
IEEE J. Solid State Circuits
Yuriy M. Greshishchev, Peter Schvan
1997 J jnl
Phase-correcting feedback system for class E power amplifier.
IEEE J. Solid State Circuits
Tirdad Sowlati, Yuriy M. Greshishchev, C. André T. Salama
1995 B conf
Linear transmitter design using high efficiency Class E power amplifier.
PIMRC
Tirdad Sowlati, Yuriy M. Greshishchev, C. André T. Salama, Gord Rabjohn, John Sitch