Yunhao Zhou - RankMe

22 papers A* 4A 2Journal 15Unranked 1

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior. AAAI Ruiyang Ma, Yunhao Zhou, Yipeng Wang, Yi Liu, Zhengyuan Shi, Ziyang Zheng, Kexin Chen, Zhiqiang He, Lingwei Yan, Gang Chen, Qiang Xu, Guojie Luo
2025	J	`jnl`	A data-centric chip design agent framework for Verilog code generation. ACM Trans. Design Autom. Electr. Syst. Kaiyan Chang, Wenlong Zhu, Kun Wang, Xinyang He, Nan Yang, Zhirong Chen, Dantong Jin, Cangyuan Li, Yunhao Zhou, Hao Yan, Zhuoliang Zhao, Yuan Cheng, Mengdi Wang, Shengwen Liang, Yinhe Han, Xiaowei Li, Huawei Li, Ying Wang
2025	J	`jnl`	DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis. CoRR Zeju Li, Changran Xu, Zhengyuan Shi, Zedong Peng, Yi Liu, Yunhao Zhou, Lingfeng Zhou, Chengyu Ma, Jianyuan Zhong, Xi Wang, Jieru Zhao, Zhufei Chu, Xiaoyan Yang, Qiang Xu
2025	—	`conf`	DeepRTL2: A Versatile Model for RTL-Related Tasks. ACL (Findings) Yi Liu, Hongji Zhang, Yunhao Zhou, Zhengyuan Shi, Changran Xu, Qiang Xu
2025	J	`jnl`	DeepRTL2: A Versatile Model for RTL-Related Tasks. CoRR Yi Liu, Hongji Zhang, Yunhao Zhou, Zhengyuan Shi, Changran Xu, Qiang Xu
2025	A*	`conf`	DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model. ICLR Yi Liu, Changran Xu, Yunhao Zhou, Zeju Li, Qiang Xu
2025	J	`jnl`	DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model. CoRR Yi Liu, Changran Xu, Yunhao Zhou, Zeju Li, Qiang Xu
2025	J	`jnl`	DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior. CoRR Ruiyang Ma, Yunhao Zhou, Yipeng Wang, Yi Liu, Zhengyuan Shi, Ziyang Zheng, Kexin Chen, Zhiqiang He, Lingwei Yan, Gang Chen, Qiang Xu, Guojie Luo
2025	J	`jnl`	ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA. CoRR Zhengyuan Shi, Zeju Li, Chengyu Ma, Yunhao Zhou, Ziyang Zheng, Jiawei Liu, Hongyang Pan, Lingfeng Zhou, Kezhi Li, Jiaying Zhu, Lingwei Yan, Zhiqiang He, Chenhao Xue, Wentao Jiang, Fan Yang, Guangyu Sun, Xiaoyan Yang, Gang Chen, Chuan Shi, Zhufei Chu, Jun Yang, Qiang Xu
2025	A	`conf`	MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs. ICCAD Chenchen Zhao, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu
2025	J	`jnl`	MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs. CoRR Chenchen Zhao, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Guangyu Sun, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu
2025	A*	`conf`	Speculative Decoding for Verilog: Speed and Quality, All in One. DAC Changran Xu, Yi Liu, Yunhao Zhou, Shan Huang, Ningyi Xu, Qiang Xu
2025	J	`jnl`	Speculative Decoding for Verilog: Speed and Quality, All in One. CoRR Changran Xu, Yi Liu, Yunhao Zhou, Shan Huang, Ningyi Xu, Qiang Xu
2024	J	`jnl`	C^0 Generalized Coons Patches for High-order Cage-based Deformation. ACM Trans. Graph. Kaikai Qin, Yunhao Zhou, Chenhao Ying, Yajuan Li, Chongyang Deng
2024	A*	`conf`	Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. DAC Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2024	J	`jnl`	Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. CoRR Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2024	A	`conf`	Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. ICCAD Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang
2024	J	`jnl`	Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. CoRR Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang
2023	J	`jnl`	Moving Towards Centers: Re-Ranking With Attention and Memory for Re-Identification. IEEE Trans. Multim. Yunhao Zhou, Yi Wang, Lap-Pui Chau
2022	J	`jnl`	Rethinking and Designing a High-Performing Automatic License Plate Recognition Approach. IEEE Trans. Intell. Transp. Syst. Yi Wang, Zhen-Peng Bian, Yunhao Zhou, Lap-Pui Chau
2021	J	`jnl`	Moving Towards Centers: Re-ranking with Attention and Memory for Re-identification. CoRR Yunhao Zhou, Yi Wang, Lap-Pui Chau
2020	J	`jnl`	Rethinking and Designing a High-performing Automatic License Plate Recognition Approach. CoRR Yi Wang, Zhen-Peng Bian, Yunhao Zhou, Lap-Pui Chau