Yung-Yuan Chen

33 papers C 2Misc 3Journal 10Unranked 18

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	An Effective Integrated Reliability Modeling for Safety-Critical FlexRay Communication Systems. Qual. Reliab. Eng. Int. Kuen-Long Lu, Yung-Yuan Chen
2024	J	`jnl`	Development of an Effective Corruption-Related Scenario-Based Testing Approach for Robustness Verification and Enhancement of Perception Systems in Autonomous Driving. Sensors Hsiang Huang, Yung-Yuan Chen
2021	J	`jnl`	Intelligent Traffic Control System by Using Image Information. CoRR Zong-Ming Lin, Cheng-Yang Chang, Chin-Yu Hu, Yung-Yuan Chen
2021	—	`conf`	Model-based design, analysis and assessment framework for safety-critical systems. DSN (Supplements) Kuen-Long Lu, Yung-Yuan Chen
2021	J	`jnl`	SoC-Level Safety-Oriented Design Process in Electronic System Level Development Environment. J. Circuits Syst. Comput. Kuen-Long Lu, Yung-Yuan Chen
2020	—	`conf`	Analysis of the Effect of Automotive Ethernet Camera Image Quality on Object Detection Models. ICAIIC Hsiang Huang, Kuan-Chung Chen, Po-Yi Li, Yung-Yuan Chen
2020	—	`conf`	Automotive Ethernet-Based Black Box System. ICAIIC Yan-Xun LU, Yung-Yuan Chen, Wen-Nan Fang
2019	—	`conf`	ISO 26262 ASIL-Oriented Hardware Design Framework for Safety-Critical Automotive Systems. ICCVE Kuen-Long Lu, Yung-Yuan Chen
2018	—	`conf`	FMEDA-Based Fault Injection and Data Analysis in Compliance with ISO-26262. DSN Workshops Kuen-Long Lu, Yung-Yuan Chen, Li-Ren Huang
2016	—	`conf`	An Effective Two-Level Redundancy Approach for FlexRay Network Systems. DSN Workshops Yung-Yuan Chen, Kuen-Long Leu
2015	—	`conf`	An effective multiple-level fault-tolerant framework for FlexRay network systems. ICCVE Hsiang Huang, Kuen-Long Leu, Yung-Yuan Chen
2015	—	`conf`	An intelligent brake-by-wire system design and analysis in accordance with ISO-26262 functional safety standard. ICCVE Kuen-Long Leu, Hsiang Huang, Yung-Yuan Chen, Li-Ren Huang, Kung-Ming Ji
2012	—	`conf`	ECU-level fault-tolerant framework for safety-critical FlexRay network systems. ICTC Yung-Yuan Chen, Chia-Ming Lyu
2012	—	`conf`	Generic Reliability Analysis for Safety-Critical FlexRay Drive-By-Wire Systems. ICCVE Kuen-Long Leu, Jwu-E Chen, Chin-Long Wey, Yung-Yuan Chen
2010	J	`jnl`	Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment. Microprocess. Microsystems Yung-Yuan Chen, Kuen-Long Leu
2009	—	`conf`	Robustness investigation of the FlexRay system. SIES Kuen-Long Leu, Chin-Long Wey, Jwu-E Chen, Yung-Yuan Chen
2009	—	`conf`	SoC-level risk assessment using FMEA approach in system design with SystemC. SIES Yung-Yuan Chen, Chung-Hsien Hsu, Kuen-Long Leu
2008	—	`conf`	An Estimation Model of Vulnerability for Embedded Microprocessors. SSIRI Yung-Yuan Chen, Shu-Hao Hsu, Kuen-Long Leu
2008	C	`conf`	An Online Control Flow Check for VLIW Processor. PRDC Hung-Chuan Lai, Shi-Jinn Horng, Yung-Yuan Chen
2008	—	`conf`	System-Bus Fault Injection Framework in SystemC Design Platform. SSIRI Kun-Chun Chang, Yi-Chinag Wang, Chung-Hsien Hsu, Kuen-Long Leu, Yung-Yuan Chen
2006	C	`conf`	Fault-Tolerant VLIW Processor Design and Error Coverage Analysis. EUC Yung-Yuan Chen, Kuen-Long Leu, Chao-Sung Yeh
2006	—	`conf`	Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors. CDES Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin
2005	J	`jnl`	Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring. IEEE Trans. Computers Yung-Yuan Chen
2004	—	`conf`	Incorporating Signature-Monitoring Technique in VLIW Processors. DFT Yung-Yuan Chen, Kun-Feng Chen
2003	—	`conf`	An Integrated Fault-Tolerant Design Framework for VLIW Processors. DFT Yung-Yuan Chen, Shi-Jinn Horng, Hung-Chuan Lai
1999	Misc	`conf`	Concurrent Detection of Processor Control Errors by Hybrid Signature Monitoring. EDCC Yung-Yuan Chen
1997	J	`jnl`	A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors. IEEE Trans. Computers Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng
1995	Misc	`conf`	An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. VLSI Design Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen
1994	Misc	`conf`	An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. EDCC Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou
1994	J	`jnl`	Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy. IEEE Trans. Computers Yung-Yuan Chen, Shambhu J. Upadhyaya
1993	J	`jnl`	Reliability, Reconfiguration, and Spare Allocation Issues in Binary-Tree Architectures Based on Multiple-Level Redundancy. IEEE Trans. Computers Yung-Yuan Chen, Shambhu J. Upadhyaya
1993	J	`jnl`	Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy. IEEE Trans. Computers Yung-Yuan Chen, Shambhu J. Upadhyaya
1990	—	`conf`	An analysis of a reconfigurable binary tree architecture based on multiple-level redundancy. FTCS Yung-Yuan Chen, Shambhu J. Upadhyaya