Yung-Hui Chung

36 papers C 7Journal 13Unranked 16

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A 12-bit SAR ADC Utilizing Background Capacitor Calibration with LLM-LMS Algorithm. ISCAS Chung-Wei Lin, Yung-Hui Chung
2024	C	`conf`	A 105-dB SFDR 16-bit SAR ADC with a Window Capacitor Calibration Scheme. ISCAS Qi-Fen Zeng, Chia-Hui Tien, Yung-Hui Chung
2024	C	`conf`	A 10b 400MS/s 2x-Time-Interleaved 2-Then-1b/Cycle SAR ADC in 90nm CMOS. ISCAS Wei-Chung Lin, Yung-Chi Chang, Yung-Hui Chung
2024	—	`conf`	A 12b Dual-Mode SAR ADC for Bio-Medical Applications. BioCAS Yung-Hui Chung, Jyun-Hau Kuo
2024	—	`conf`	A 91.7-dB SNDR Discrete-Time Zoom ADC with a 20-kHz BW in 180-nm CMOS. APCCAS Zi-Chi Lin, Chun-Yang Chiu, Yung-Hui Chung
2023	—	`conf`	A 90-dB DR Discrete-Time Delta-Sigma Modulator for Audio Applications. ISOCC Hou-Hsuan Lin, Jia-Fong Shih, Yung-Hui Chung
2022	J	`jnl`	A 16-Bit Calibration-Free SAR ADC With Binary-Window and Capacitor-Swapping DAC Switching Schemes. IEEE Trans. Circuits Syst. I Regul. Pap. Yung-Hui Chung, Chia-Hui Tien, Qi-Feng Zeng
2021	—	`conf`	A Resistor-Less CMOS Bandgap Reference with High-Order Temperature Compensation. APCCAS Yung-Hui Chung, Jia-Fong Shih, Yu-Hsiang Wang
2021	—	`conf`	An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique. VLSI-DAT Bo-Wei Chen, Yung-Hui Chung, Chia-Ming Tsai
2020	—	`conf`	A 12-bit 100-kS/s SAR ADC for IoT Applications. VLSI-DAT Yung-Hui Chung, Qi-Feng Zeng
2020	J	`jnl`	A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Yung-Hui Chung, Qi-Feng Zeng, Yi-Shen Lin
2020	J	`jnl`	A 3-mW 12b 160-MS/s 2-Way Time-Interleaved Subrange SAR ADC in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Yung-Hui Chung, Wei-Shu Rih
2019	—	`conf`	A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS. APCCAS Yung-Hui Chung, Chia-Hui Tien, Qi-Feng Zeng
2019	J	`jnl`	A 12-Bit 100-MS/s Subrange SAR ADC With a Foreground Offset Tracking Calibration Scheme. IEEE Trans. Circuits Syst. II Express Briefs Yung-Hui Chung, Ya-Mien Hsu
2019	C	`conf`	A 12-Bit Synchronous-SAR ADC for IoT Applications. ISCAS Yung-Hui Chung, Min-Sheng Chiang
2019	—	`conf`	A 12-bit Domino ADC with a Background Offset Calibration Scheme. APCCAS Yung-Hui Chung
2018	J	`jnl`	A 12-bit 10-MS/s SAR ADC with a binary-window DAC switching scheme in 180-nm CMOS. Int. J. Circuit Theory Appl. Yung-Hui Chung, Chia-Wei Yen, Pei-Kang Tsai
2018	—	`conf`	A 12-bit 20-MS/s SAR ADC With Fast-Binary-Window DAC Switching in 180nm CMOS. APCCAS Yung-Hui Chung, Yi-Shen Lin, Qi-Feng Zeng
2018	J	`jnl`	A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme. IEEE Trans. Very Large Scale Integr. Syst. Yung-Hui Chung, Chia-Wei Yen, Pei-Kang Tsai, Bo-Wei Chen
2018	—	`conf`	A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration. A-SSCC Yung-Hui Chung, Chia-Yi Hu, Che-Wei Chang
2018	J	`jnl`	A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Yung-Hui Chung, Wei-Shu Rih, Che-Wei Chang
2017	—	`conf`	A 10-bit 100-MS/s SAR ADC with capacitor swapping technique in 90-nm CMOS. VLSI-DAT Yung-Hui Chung, Song-You Shih
2017	—	`conf`	A 12-bit 160-MS/s ping-pong subranged-SAR ADC in 65nm CMOS. ISOCC Yung-Hui Chung, Ya-Mien Hsu, Chia-Wei Yen, Wei-Shu Rih
2017	J	`jnl`	A 5-bit 1-GS/s binary-search ADC in 90-nm CMOS. Microelectron. J. Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chih Yeh
2017	—	`conf`	A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS. ISOCC Yung-Hui Chung, Wei-Shu Rih
2017	J	`jnl`	An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Yung-Hui Chung, Chia-Wei Yen
2016	J	`jnl`	A 24- μW 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Yung-Hui Chung, Chia-Wei Yen, Meng-Hsuan Wu
2016	—	`conf`	A 5-b 1-GS/s binary-search ADC in 90nm CMOS. APCCAS Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chih Yeh
2016	C	`conf`	A PVT-tracking metastability detector for asynchronous ADCs. ISCAS Yung-Hui Chung, Chia-Wei Yen
2015	J	`jnl`	A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Yung-Hui Chung, Meng-Hsuan Wu, Hung-Sung Li
2015	J	`jnl`	A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Yung-Hui Chung, Jieh-Tsorng Wu
2015	—	`conf`	A 5-b 1-GS/s 2.7-mW binary-search ADC in 90nm digital CMOS. SoCC Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chin Yeh
2014	C	`conf`	Perturbation-based digital background calibration technique for pipelined ADCs. ISCAS Yung-Hui Chung
2013	—	`conf`	A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching. CICC Yung-Hui Chung, Meng-Hsuan Wu, Hung-Sung Li
2013	C	`conf`	The swapping binary-window DAC switching technique for SAR ADCs. ISCAS Yung-Hui Chung
2010	J	`jnl`	A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC. IEEE J. Solid State Circuits Yung-Hui Chung, Jieh-Tsorng Wu