Yung-Chia Lin

14 papers B 1Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2023 J jnl
Guest Editorial: Special Issue on Systems Optimizations for DSP and AI Applications.
J. Signal Process. Syst.
Kuan-Hsun Chen, Yung-Chia Lin, Jenq-Kuen Lee
2019 — conf
Case Study: Support OpenCL Complex Class for Baseband Computing.
IWOCL
Chia-Hsuan Chang, Chun-Chieh Yang, Jenq-Kuen Lee, Yung-Chia Lin
2019 J jnl
Guest Editorial: Special Issue on Embedded Multicore Applications and Optimization.
J. Signal Process. Syst.
Yung-Chia Lin, Jenq-Kuen Lee, François Bodin
2009 J jnl
LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files.
Concurr. Comput. Pract. Exp.
Chia-Han Lu, Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee
2008 — conf
An MILP-based wire spreading algorithm for PSM-aware layout modification.
ASP-DAC
Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang
2008 J jnl
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores.
J. Signal Process. Syst.
Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee
2008 J jnl
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch.
J. Signal Process. Syst.
Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee
2007 J jnl
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains.
J. Supercomput.
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang
2007 J jnl
PALF: compiler supports for irregular register files in clustered VLIW DSP processors.
Concurr. Comput. Pract. Exp.
Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee
2006 B conf
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors.
RTCSA
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, Shih-Chang Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, Jenq Kuen Lee
2005 — conf
Compiler Supports and Optimizations for PAC VLIW DSP Processors.
LCPC
Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen, Jenq Kuen Lee
2005 — conf
System-level design space exploration for security processor prototyping in analytical approaches.
ASP-DAC
Yung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee
2004 — conf
Power-Aware Scheduling for Parallel Security Processors with Analytical Models.
LCPC
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang
2002 — conf
Compiler Optimizations with DSP-Specific Semantic Descriptions.
LCPC
Yung-Chia Lin, Yuan-Shin Hwang, Jenq Kuen Lee