Yun Chiu - RankMe

59 papers C 2Journal 33Unranked 24

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	An IF-Sampling CMOS S/H Calibration Technique With Analog HPF Slope Estimation. IEEE Trans. Circuits Syst. II Express Briefs Yanqing Li, Yun Chiu
2021	J	`jnl`	Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Yun Chiu, Man-Kay Law, Nagendra Krishnapura, Jason T. Stauth, Jeffrey S. Walling
2020	J	`jnl`	A Compact Calibration Model for Linearizing CMOS Sample-and-Hold Circuits. IEEE Trans. Circuits Syst. Yanqing Li, Yuan Zhou, Yun Chiu
2019	J	`jnl`	A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC. IEEE J. Solid State Circuits Yuan Zhou, Benwei Xu, Yun Chiu
2019	J	`jnl`	A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS. IEEE J. Solid State Circuits Hongda Xu, Hai Huang, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu
2018	J	`jnl`	A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS. IEEE J. Solid State Circuits Shuang Zhu, Bo Wu, Yongda Cai, Yun Chiu
2018	J	`jnl`	A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS. IEEE J. Solid State Circuits Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu
2017	—	`conf`	28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation. ISSCC Hai Huang, Sudipta Sarkar, Brian Elies, Yun Chiu
2017	—	`conf`	28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS. ISSCC Hongda Xu, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu
2017	J	`jnl`	A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer. IEEE J. Solid State Circuits Hai Huang, Ling Du, Yun Chiu
2017	J	`jnl`	A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS. IEEE J. Solid State Circuits Benwei Xu, Yuan Zhou, Yun Chiu
2017	J	`jnl`	A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation. IEEE J. Solid State Circuits Hai Huang, Hongda Xu, Brian Elies, Yun Chiu
2017	—	`conf`	An 8b 1.39GS/S 0.85V two-step ADC with background comparator offset calibration. MWSCAS Sudipta Sarkar, Benwei Xu, Brian Elies, Yun Chiu
2016	—	`conf`	15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS. ISSCC Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu
2016	—	`conf`	A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS. VLSI Circuits Benwei Xu, Yuan Zhou, Yun Chiu
2016	J	`jnl`	A 24.7 mW 65 nm CMOS SAR-Assisted CT ΔΣ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR. IEEE J. Solid State Circuits Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu
2016	J	`jnl`	A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM. IEEE J. Solid State Circuits Shuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu
2016	—	`conf`	A smart ECG sensor with in-situ adaptive motion-artifact compensation for dry-contact wearable healthcare devices. ISQED Shuang Zhu, Jingyi Song, Balaji Chellappa, Ali Enteshari, Tuo Shan, Mengxun He, Yun Chiu
2015	—	`conf`	A 0.073-mm CICC Shuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu
2015	—	`conf`	A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer. A-SSCC Hai Huang, Ling Du, Yun Chiu
2015	J	`jnl`	A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector. IEEE J. Solid State Circuits Yuan Zhou, Benwei Xu, Yun Chiu
2015	J	`jnl`	A 40 nm CMOS Derivative-Free IF Active-RC BPF With Programmable Bandwidth and Center Frequency Achieving Over 30 dBm IIP3. IEEE J. Solid State Circuits Bo Wu, Yun Chiu
2015	J	`jnl`	Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Benwei Xu, Yun Chiu
2015	J	`jnl`	PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Sudipta Sarkar, Yuan Zhou, Brian Elies, Yun Chiu
2014	—	`conf`	A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration. VLSIC Yuan Zhou, Benwei Xu, Yun Chiu
2014	J	`jnl`	A 15-MHz Bandwidth 1-0 MASH Σ Δ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR. IEEE J. Solid State Circuits Seung-Chul Lee, Yun Chiu
2014	—	`conf`	A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system. CICC Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu
2014	—	`conf`	An 85-225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOS. CICC Bo Wu, Yun Chiu
2014	J	`jnl`	IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration. IEEE Trans. Circuits Syst. II Express Briefs Guanhua Wang, Foti Kacani, Yun Chiu
2014	—	`conf`	PN-assisted deterministic digital calibration of split two-step ADC to over 14-bit accuracy. MWSCAS Sudipta Sarkar, Yuan Zhou, Yun Chiu
2013	C	`conf`	Background calibration of time-interleaved ADC using direct derivative information. ISCAS Benwei Xu, Yun Chiu
2013	—	`conf`	Digital calibration of inter-stage nonlinear errors in pipelined SAR ADC. MWSCAS Yuan Zhou, Yun Chiu
2013	—	`conf`	Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering. CICC Guanhua Wang, Yun Chiu
2012	—	`conf`	A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration. CICC Wenbo Liu, Pingli Huang, Yun Chiu
2012	J	`jnl`	A 15 MHz to 600 MHz, 20 mW, 0.38 mm IEEE Trans. Very Large Scale Integr. Syst. Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic
2012	—	`conf`	An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration. VLSIC Seung-Chul Lee, Brian Elies, Yun Chiu
2012	J	`jnl`	Time-Interleaved Analog-to-Digital Conversion With Online Adaptive Equalization. IEEE Trans. Circuits Syst. I Regul. Pap. Wenbo Liu, Yun Chiu
2011	J	`jnl`	A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration. IEEE J. Solid State Circuits Wenbo Liu, Pingli Huang, Yun Chiu
2011	J	`jnl`	Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Seung-Chul Lee, Yun Chiu
2011	J	`jnl`	Equalization techniques for nonlinear analog circuits. IEEE Commun. Mag. Yun Chiu
2011	J	`jnl`	SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration. IEEE J. Solid State Circuits Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu
2010	—	`conf`	A 12b 22.5/45MS/s 3.0mW 0.059mm ISSCC Wenbo Liu, Pingli Huang, Yun Chiu
2010	—	`conf`	A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over -80-dB IM3. CICC Peiyuan Wan, Yun Chiu, Pingfen Lin
2010	J	`jnl`	A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling. IEEE J. Solid State Circuits Richard Tseng, Hao Li, Dae Hyun Kwon, Yun Chiu, Ada S. Y. Poon
2010	J	`jnl`	A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion. IEEE Trans. Circuits Syst. II Express Briefs Bei Peng, Hao Li, Seung-Chul Lee, Pingfen Lin, Yun Chiu
2010	J	`jnl`	An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs. IEEE Trans. Circuits Syst. II Express Briefs Bei Peng, Hao Li, Pingfen Lin, Yun Chiu
2010	J	`jnl`	Digital Calibration of Nonlinear Memory Errors in Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Seung-Chul Lee, Yun Chiu
2010	J	`jnl`	Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier. IEEE J. Solid State Circuits Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu
2010	—	`conf`	SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration. CICC Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu
2009	—	`conf`	A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. ISSCC Wenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu
2009	J	`jnl`	A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation. IEEE J. Sel. Top. Signal Process. Hao Li, Dae Hyun Kwon, Deming Chen, Yun Chiu
2009	—	`conf`	CMOS RF transmitter with integrated power amplifier utilizing digital equalization. CICC Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu
2008	—	`conf`	A 15 MHz - 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS. ESSCIRC Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic
2008	J	`jnl`	A Mixed-Signal Vector Modulator for Eigenbeamforming Receivers. IEEE Trans. Circuits Syst. II Express Briefs Richard Tseng, Ada S. Y. Poon, Yun Chiu
2008	—	`conf`	Background ADC calibration in digital domain. CICC Cheongyuen W. Tsang, Yun Chiu, Johan P. Vanderhaegen, Sebastian Hoyos, Charles Chen, Robert W. Brodersen, Borivoje Nikolic
2007	C	`conf`	A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs. ISCAS Pingli Huang, Yun Chiu
2005	—	`conf`	Scaling of analog-to-digital converters into ultra-deep-submicron CMOS. CICC Yun Chiu, Borivoje Nikolic, Paul R. Gray
2004	J	`jnl`	A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR. IEEE J. Solid State Circuits Yun Chiu, Paul R. Gray, Borivoje Nikolic
2004	J	`jnl`	Least mean square adaptive digital background calibration of pipelined analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. Yun Chiu, Cheongyuen W. Tsang, Borivoje Nikolic, Paul R. Gray