Yun-Shiang Shu

20 papers Journal 4Unranked 16
YearRankTypeTitle / Venue / Authors
2025 — conf
24.6 A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC.
ISSCC
Cheng-En Hsieh, Gabriele Manganaro, Sheng-Hui Liao, Jack Weng, Tsun-Yuan Fan, Alec Chin, Tsung-Chih Hung, Jonathan X. Wu, Chi-Lun Lo, Andy Pan, Ming-Hang Hsieh, Yun-Shiang Shu, Wei-Hsin Tseng, Kuan-Dar Chen
2022 — conf
Design Techniques for High Linearity and Dynamic Range Digital to Analog Converters.
CICC
Ayman Shabra, Yun-Shiang Shu, Shon-Hang Wen, Kuan-Dar Chen
2022 — conf
Introduction of Noise-Shaping SAR ADCs.
VLSI-DAT
Yun-Shiang Shu
2021 — conf
F2: Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits.
ISSCC
Youngcheol Chae, Yun-Shiang Shu, Jens Anders, Viola Schaffer, Takashi Oshima, Marco Corsi
2020 — conf
26.1 A 4.5mm
ISSCC
Yun-Shiang Shu, Zhi-Xin Chen, Yu-Hong Lin, Su-Hao Wu, Wei-Hsiang Huang, Albert Yen-Chih Chiou, Chang-Yang Huang, Hung-Yi Hsieh, Fan-Wei Liao, Teng-Feng Zou, Ping Chen
2020 — conf
9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s.
ISSCC
Su-Hao Wu, Yun-Shiang Shu, Albert Yen-Chih Chiou, Wei-Hsiang Huang, Zhi-Xin Chen, Hung-Yi Hsieh
2019 — conf
An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS.
ISSCC
Tien-Yu Lo, Chan-Hsiang Weng, Hung-Yi Hsieh, Yun-Shiang Shu, Pao-Cheng Chiu
2019 — conf
An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range.
VLSI Circuits
Wei-Hsiang Huang, Su-Hao Wu, Zhi-Xin Chen, Yun-Shiang Shu
2016 — conf
27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS.
ISSCC
Yun-Shiang Shu, Liang-Ting Kuo, Tien-Yu Lo
2016 J jnl
An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS.
IEEE J. Solid State Circuits
Yun-Shiang Shu, Liang-Ting Kuo, Tien-Yu Lo
2015 — conf
A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring.
A-SSCC
Liang-Ting Kuo, Chun-Chih Hou, Meng-Hsuan Wu, Yun-Shiang Shu
2013 — conf
A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer.
ISSCC
Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu
2013 — conf
A background calibration technique for fully dynamic flash ADCs.
VLSI-DAT
Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu
2012 — conf
A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators.
VLSIC
Yun-Shiang Shu
2010 J jnl
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators.
IEEE J. Solid State Circuits
Yun-Shiang Shu, Junpei Kamiishi, Koji Tomioka, Koichi Hamashita, Bang-Sup Song
2009 J jnl
A 10∼15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration.
IEEE J. Solid State Circuits
Yun-Shiang Shu, Moon-Jung Kyung, Wei-Ming Lee, Bang-Sup Song, Bedabrata Pain
2009 — conf
A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator.
CICC
Junpei Kamiishi, Yun-Shiang Shu, Koji Tomioka, Koichi Hamashita, Bang-Sup Song
2008 — conf
A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration.
CICC
Yun-Shiang Shu, Moon-Jung Kyung, Wei-Ming Lee, Bang-Sup Song, Bedabrata Pain
2008 J jnl
A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering.
IEEE J. Solid State Circuits
Yun-Shiang Shu, Bang-Sup Song
2008 — conf
A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection.
ISSCC
Yun-Shiang Shu, Bang-Sup Song, Kantilal Bacrania