Yun-Nan Chang

32 papers C 4Misc 2Journal 12Unranked 14
YearRankTypeTitle / Venue / Authors
2025 — conf
Hardware-Software Co-Design for Efficient LLM Inference on PCIe-Based FPGAs Using Coarse-Grained Systolic Arrays.
SOCC
Yun-Nan Chang
2023 — conf
Design of Low-cost IOU Circuit for Post-processing of Object Detection.
GCCE
Yun-Nan Chang
2019 — conf
Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination.
ICEIC
Yun-Nan Chang, Guan-Jhen Chen
2019 — conf
Scaling Bit-Flexible Neural Networks.
ISOCC
Yun-Nan Chang, Yu-Tang Tin
2017 C conf
A fast ray tracing scheme for dynamic scenes.
CoDIT
Yun-Nan Chang, Chin-Lun Yang
2016 — conf
Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generator.
NEWCAS
Yun-Nan Chang
2015 J jnl
An Efficient Curve-Scanline Intersection Locator Design for 2D Graphics Rendering.
J. Signal Process. Syst.
Yun-Nan Chang, Ting-Chi Tong
2015 — conf
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support.
VLSI-DAT
Hsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee
2014 — conf
Design of a 2D graphics front-end rendering processor.
ASAP
Yun-Nan Chang, Ting-Chi Tong
2013 Misc conf
Architectures for digital filters using stochastic computing.
ICASSP
Yun-Nan Chang, Keshab K. Parhi
2013 J jnl
Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer.
IEEE Trans. Very Large Scale Integr. Syst.
Ting-Chi Tong, Yun-Nan Chang
2013 — conf
Two-level hierarchical fill-buffer for graphics rendering systems.
NEWCAS
Yun-Nan Chang
2010 J jnl
A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver.
IEEE Trans. Very Large Scale Integr. Syst.
Yun-Nan Chang
2010 J jnl
Digit-Serial Pipeline Sorter Architecture.
J. Signal Process. Syst.
Yun-Nan Chang
2009 J jnl
A Fast Spline Curve Rendering Accelerator Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Yun-Nan Chang
2009 — conf
A Lossless Buffer Compression Scheme for 3D Graphic System.
CGVR
Yun-Nan Chang, Ting-Chi Tong
2009 — conf
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics.
ASP-DAC
Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang
2008 J jnl
A low-cost dual-mode deinterleaver design.
IEEE Trans. Consumer Electron.
Yun-Nan Chang
2008 J jnl
An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization.
J. Signal Process. Syst.
Yun-Nan Chang, Ting-Chi Tong
2008 J jnl
An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design.
IEEE Trans. Circuits Syst. II Express Briefs
Yun-Nan Chang
2005 — conf
Design of an efficient memory-based DVB-T channel decoder.
ISCAS (5)
Yun-Nan Chang
2003 J jnl
An Efficient In-Place VLSI Architecture for Viterbi Algorithm.
J. VLSI Signal Process.
Yun-Nan Chang
2003 J jnl
An efficient pipelined FFT architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Yun-Nan Chang, Keshab K. Parhi
2003 — conf
Design of soft-output Viterbi decoders with hybrid trace-back processing.
ISCAS (2)
Yun-Nan Chang
2000 J jnl
A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder.
IEEE J. Solid State Circuits
Yun-Nan Chang, Hiroshi Suzuki, Keshab K. Parhi
1999 — conf
Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems.
CICC
Hiroshi Suzuki, Yun-Nan Chang, Keshab K. Parhi
1999 Misc conf
Low-power bit-serial Viterbi decoder for next generation wide-band CDMA systems.
ICASSP
Hiroshi Suzuki, Yun-Nan Chang, Keshab K. Parhi
1998 J jnl
Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units.
J. VLSI Signal Process.
Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi
1998 C conf
High-performance digit-serial complex-number multiplier-accumulator.
ICCD
Yun-Nan Chang, Keshab K. Parhi
1997 C conf
Design and Implementation of Low-Power Digit-Serial Multipliers.
ICCD
Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi
1996 — conf
Loop-List Scheduling for Heterogeneous Functional Units.
Great Lakes Symposium on VLSI
Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi
1996 C conf
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.
ICCD
Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang